Temperature sensing circuit, driving apparatus, and printer

ABSTRACT

A temperature-sensing circuit has a pair of bipolar transistors of different sizes, exposed to the temperature to be sensed. A current mirror circuit, or an operational amplifier and another bipolar transistor, is used to sense the difference between the base-emitter voltages of the bipolar transistors and generate a corresponding output current, which is converted to a voltage output signal. This temperature-sensing circuit can be integrated into a driving circuit to sense the temperature of the driven elements and compensate for temperature effects. In a printer, the temperature-sensing circuit can be used for temperature compensation of dot-forming elements.

BACKGROUND OF THE INVENTION

The present invention relates to a temperature-sensing circuit, to adriving apparatus using this temperature-sensing circuit in selectivelyand cyclically driving a group of driven elements such as a row oflight-emitting diodes employed in an electrophotographic printer, a rowof resistive heating elements employed in a thermal printer, or an arrayof display elements employed in a display device, and to a printeremploying this type of driving apparatus.

In the following description, the driven elements will be light-emittingdiodes or LEDs employed in an electrophotographic printer.

In a conventional electrophotographic printer, for example, anelectrically charged photosensitive drum is selectively illuminated,responsive to the data to be printed, to form a latent electrostaticimage, which is developed by application of toner particles to form atoner image. The toner image is then transferred to paper and fused ontothe paper.

FIG. 52 is a block diagram of the control circuitry of a conventionalelectrophotographic printer. FIG. 53 is a timing diagram illustratingthe operation of the conventional electrophotographic printer.

The printing control unit 1 in FIG. 52 comprises a microprocessor,read-only memory (ROM), random-access memory (RAM), input-output ports,timers, and other elements disposed in the printing engine of theprinter. The printing control unit 1 receives a control signal SG1 and adot data signal SG2 from a higher-order controller, and controls theprinting operations performed by the printing engine. The dot datasignal SG2 is a one-dimensional digital signal representing atwo-dimensional bit map of picture elements (pixels), referred to belowas dots.

Upon receiving a print command via control signal SG1, the printingcontrol unit 1 first checks a temperature sensor 23 to determine whetherthe fuser 22 is within the necessary temperature range. If the fuser 22is not within the necessary temperature range, the printing control unit1 activates a heater 22a built into the fuser 22. When the fuser 22reaches the necessary temperature, the printing control unit 1 activatesa driver 2 that drives a stepping motor or pulse motor (PM) 3 used inthe developing and transfer process, and activates a charge signal SGCthat switches on a high-voltage power source 25 that charges tonerparticles in a developer unit 27.

The presence or absence of paper and the size of the paper are detectedby a paper sensor 8 and size sensor 9. If paper is present, the printingcontrol unit 1 activates a driver 4 that drives another pulse motor (PM)5. This motor is first driven in reverse by a certain amount, untilpaper is detected by a pick-up sensor 6, then driven forward to feed thepaper into the printing engine.

When the paper has been fed to the necessary position, the printingcontrol unit 1 sends timing signals SG3 (including horizontal andvertical synchronization signals) to the higher-order controller, andbegins receiving the dot data signal SG2, which the higher-ordercontroller generates on a page-at-a-time basis. The dot data signal SG2is supplied as a data signal HD-DATA to an LED head 19 comprising a rowof LEDs, with one LED per dot. The transfer of dot data into the LEDhead 19 is synchronized with a clock signal (HD-CLK). The dot data willbe referred to below as driving data, since they determine whether eachLED is driven or not.

After sufficient driving data (HD-DATA) for one horizontal dot line havebeen transferred into the LED head 19, the printing control unit 1 sendsthe LED head 19 a load signal (HD-LOAD), causing the driving data to belatched in the LED head 19. The LED head 19 can then print this linewhile receiving driving data for the next line.

The LED head 19 prints the line by illuminating a photosensitive drum(not visible) which has been precharged to a negative electricalpotential. The potential level of illuminated dots rises, creating alatent dot image. The toner in the developer unit 27 is also charged toa negative potential, so toner particles are electrostatically attractedto the illuminated dots, creating a toner image.

The LEDs are turned on and off in synchronization with a strobe signal(HD-STB-N). FIG. 53 illustrates the timing of this signal and othersignals mentioned above. The SG3 pulses shown at the top of FIG. 53 arehorizontal synchronization pulses. FIG. 53 illustrates three successiveline-printing cycles, for printing lines N-1, N, and N+1 (where N is anarbitrary integer).

Referring again to FIG. 52, to transfer the toner image to the paper,the printing control unit 1 activates a transfer signal SG4 that turnson a high-voltage power source 26, generating a high positive voltage ina transfer unit 28. As the paper travels through a narrow gap betweenthe photosensitive drum and transfer unit 28, the toner image istransferred by electrostatic attraction to the paper.

The paper with the toner image is then transported to the fuser 22,which has been heated by the heater 22a. The heat fuses the toner to thepaper, which then passes an exit sensor 7 and is ejected from theprinter.

The printing control unit 1 controls these operations so that thehigh-voltage power source 26 is switched off except while the paper istraveling past the transfer unit 28, as detected by sensors 6 and 9.When the paper passes the exit sensor 7, the printing control unit 1also switches off the high-voltage power source 25 of the developer unit27, and stops the pulse motor (PM) 3 used in the developing and transferprocess.

The above sequence is repeated for each page.

FIG. 54 shows the structure of the conventional LED head 19 in moredetail. The driving data HD-DATA and clock signal HD-CLK are provided toa shift register comprising, for example, two thousand four hundredninety-six flip-flop circuits FF₁, FF₂, . . . , FF₂₄₉₆ (this number offlip-flop circuits is appropriate for printing on A4-size paper at threehundred dots per inch). When two thousand four hundred ninety-six bitsof driving data have been clocked into this shift register, the loadsignal HD-LOAD is activated, causing the bits to be stored in latchesLT₁, LT₂, . . . , LT₂₄₉₆. When the strobe signal HD-STB-N is driven low,bits set to the high logic level (one) turn on light-emitting diodesLD₁, LD₂, . . . , LD₂₄₉₆ by way of an inverter G₀. NAND gates G₁, G₂, .. . , G₂₄₉₆, and p-channel metal-oxide-semiconductor (MOS) transistorsTr₁, Tr₂, . . . , Tr₂₄₉₆. The symbol V_(DD) represents a power-supplypotential.

In a printer employing the LED head in FIG. 54, all of thelight-emitting diodes LD₁, LD₂, . . . , LD₂₄₉₆ that are switched on areswitched on for the same length of time, determined by the strobe signalHD-STB-N. Thus if these light-emitting diodes, or the transistors Tr₁,Tr₂, . . . , Tr₂₄₉₆, do not have perfectly uniform electricalproperties, the dots will be unevenly illuminated. This will lead todifferences in the sizes of the electrostatic dots in the latent imageformed on the photosensitive drum, hence to differences in the sizes ofthe dots printed on the page. Although different dot sizes are notreadily noticeable on pages containing only line art or text, whenphotographs or similar types of images are printed, variations in dotsize create density differences that can degrade the printing quality toan undesirable degree.

Typical differences in LED output are illustrated by the graph in FIG.55. Dot position is indicated on the horizontal axis, and optical poweron the vertical axis. The light-emitting diodes are disposed in aplurality of semiconductor chips, more specifically LED array chips CHP1to CHP26, which are driven by a like plurality of integrated drivercircuits (driver ICs) DRV1 to DRV26, as illustrated at the top of FIG.55. Ninety-six light-emitting diodes are integrated onto each LED arraychip. The LED array chips and driver ICs are interconnected by wirebonding. The driver ICs are cascaded to form a single shift register forreceiving the driving data signal HD-DATA.

The horizontal dotted lines indicate the ranges of variability of theoptical power output by the light-emitting diodes in each individual LEDarray. The horizontal dot-dash lines indicate the range of variabilityof the average optical output power of each LED array. Thus the dottedlines indicate ranges of dot-to-dot variation within each array, whilethe dot-dash lines indicate the range of chip-to-chip variation.

In U.S. patent application Ser. No. 08/694,055, the present inventor hasproposed a driving apparatus with circuitry for compensating for theabove chip-to-chip and dot-to-dot variations.

It has been found, however, that compensation for these chip-to-chip anddot-to-dot variations still does not assure perfectly uniform printedoutput. Further study has shown that printing irregularities can becaused by temperature differences between the LED array chips. LEDs emitlight with decreasing efficiency at increasing temperature, and during atypical printing job, depending on the printed data, some LED arraychips may be driven more intensively than other LED array chips. TheseLED array chips generate more heat, causing their temperature to riseand their optical output to fall. Compared with the other LED arraychips, the intensively driven LED array chips produce fainter printeddots.

To compensate for these temperature-induced printing irregularities, itbecomes necessary to detect the temperature of the individual LED arraychips accurately, but the known art offers no temperature-sensingcircuit suitable for this purpose.

SUMMARY OF THE INVENTION

It is accordingly an object of the present invention to provide atemperature-sensing circuit with a simple circuit configuration.

Another object of the invention is to provide a temperature-sensingcircuit that can be formed within a semiconductor integrated circuit.

A further object is to provide a driving apparatus that can compensatefor temperature-dependent variations in the output power of drivenelements.

A still further object is to provide a printer having printing elementsdriven by a driving apparatus, in which the printed output is notaffected by temperature variations.

A yet further object is to provide a simple circuit for driving drivenelements disposed in groups on a plurality of semiconductor chips, thatis capable of compensating for differences in the electricalcharacteristics of different driven elements in the same chip, forchip-to-chip differences in electrical characteristics, and also forchip-to-chip temperature differences.

According to a first aspect of the invention, a temperature-sensingcircuit has a pair of bipolar transistors of different sizes, bothbipolar transistors exposed to the temperature to be sensed. Thetemperature-sensing circuit also has a converting element for convertingcurrent to voltage, and a current mirror circuit comprising a pluralityof MOS transistors. The current mirror circuit supplies correspondingcurrents to the bipolar transistors and the converting element,responsive to a signal received from one of the bipolar transistors,thereby determining the base-emitter voltages of the bipolartransistors. The converting element generates a voltage output signalfrom the current supplied by the current mirror circuit. The voltageoutput signal is substantially proportional to the temperature to besensed.

According to a second aspect of the invention, a temperature-sensingcircuit comprises a pair of bipolar transistors of different sizes, bothexposed to a temperature to be sensed, and a converting element forconverting current to voltage. An operational amplifier generates anamplifier output signal according to the difference between thebase-emitter voltages of the two bipolar transistors. A third bipolartransistor supplies current to the converting element responsive to theamplifier output signal. The converting element generates a voltageoutput signal, proportional to the temperature to be sensed, from thecurrent supplied by the third bipolar transistor.

According to a third aspect of the invention, a driving apparatussupplying energy to a driven element comprises the temperature-sensingcircuit of the first or second aspect of the invention, and atemperature compensation circuit that adjusts the energy supplied to thedriven element responsive to the voltage output signal generated by thetemperature-sensing circuit.

According to a fourth aspect of the invention, a driving apparatusselectively and cyclically drives a plurality of driven elements to formdots. The driving apparatus uses the temperature-sensing circuit of thefirst or second aspect of the invention to sense the temperature of thedriven elements. A temperature compensation circuit generates a controlvoltage responsive to the voltage output signal generated by thetemperature-sensing circuit. A plurality of driving circuits supplydriving energy to the driven elements, responsive to driving dataindicating whether the driven elements are to be driven, to compensationdata for adjusting the driving energy, and to the control voltage. Thecompensation data are stored in a plurality of compensation memorycircuits. A data transfer means first transfers compensation data to thecompensation memory circuits, then transfers driving data to the drivingcircuits.

According to a fifth aspect of the invention, a printer uses the drivingapparatus of the fourth aspect to print dots. The printer preferably hasa printing control unit that receives the voltage output signal from thetemperature-sensing circuit and halts printing if the voltage outputsignal exceeds a threshold value.

According to a sixth aspect of the invention, a driving apparatusselectively and cyclically drives a plurality of driven elements to formdots. The driving apparatus has a test input terminal for receiving atest signal, and a plurality of driving circuits coupled to the testinput terminal. Each driving circuit has a main driving element forsupplying driving energy to a corresponding driven element, responsiveto driving data indicating whether the driven element is to be driven,when the test signal is inactive. The main driving element is disabledwhen the test signal is active. The driving circuit also has at leastone compensation driving element for supplying additional energy to thedriven element, responsive to compensation data. The driving apparatusalso has compensation memory circuits for storing the compensation data,and a data transfer means for first transferring the compensation datato the compensation memory circuits, then transferring the driving datato the driving circuits.

BRIEF DESCRIPTION OF THE DRAWINGS

In the accompanying drawings:

FIG. 1 is a block diagram illustrating the control IC and driver ICs ina driving apparatus according to the present invention;

FIG. 2 is a block diagram illustrating the internal structure of thecontrol IC in FIG. 1;

FIG. 3 is a block diagram showing an example of the internal structureof the mode control unit in FIG. 2;

FIG. 4 shows an example of the input and output terminals of thenon-volatile memory in FIG. 2;

FIG. 5 illustrates the circuits coupled to the data input/outputterminals of the control IC in FIG. 2;

FIG. 6 illustrates the circuits coupled to the data output terminals ofthe control IC in FIG. 2;

FIG. 7 shows an example of the internal structure of the clock controlunit in FIG. 2;

FIG. 8 shows an example of the internal structure of the counter in FIG.2;

FIG. 9 is a timing diagram illustrating the transfer of mode commanddata to the driving apparatus;

FIG. 10 shows an example of the bit assignments of mode command data;

FIG. 11 is a timing diagram illustrating the reading of data from thenon-volatile memory in the read mode;

FIG. 12 is a more detailed timing diagram illustrating the reading ofdata from the non-volatile memory;

FIG. 13 is a timing diagram illustrating the writing of data to thenon-volatile memory;

FIG. 14 is a block diagram illustrating the internal structure of thedriver ICs in FIG. 1;

FIG. 15 is a more detailed circuit diagram illustrating the structure ofthe shift register in FIG. 14, and showing connections to relatedcircuits;

FIG. 16 is a more detailed circuit diagram illustrating theinterconnections among the shift register and the groups of latchcircuits, compensation memory circuits, and driving circuits in FIG. 14;

FIG. 17 illustrates two of the latch circuits in FIG. 16;

FIG. 18 is a circuit diagram illustrating two of the compensation memorycircuits in FIG. 16;

FIG. 19 is a circuit diagram showing an example of the configuration ofthe current reference circuit in FIG. 14;

FIG. 20 is a circuit diagram illustrating the internal structure of oneof the driving circuits in FIG. 14, showing the circuitry for drivingone LED;

FIG. 21 is a graph illustrating the compensation for differences in theoptical output of the LEDs;

FIG. 22 is a circuit diagram of a timing generator circuit in the driverICs in FIG. 1;

FIG. 23 is a circuit diagram of a bit position counter circuit in thedriver ICs in FIG. 1;

FIG. 24 is a circuit diagram of a word-line decoder circuit in thedriver ICs in FIG. 1;

FIG. 25 is a timing diagram illustrating the writing of compensationdata;

FIG. 26 is a more detailed timing diagram illustrating the operation ofthe timing generator circuit, bit position counter circuit, andword-line decoder circuit;

FIG. 27 is a circuit diagram of a temperature-sensing circuit accordingto a first embodiment of the invention;

FIG. 28 is a circuit diagram of a temperature-sensing circuit accordingto a second embodiment of the invention;

FIG. 29 is a circuit diagram of a temperature-sensing circuit accordingto a third embodiment of the invention;

FIG. 30 is a timing diagram illustrating the operation of the thirdembodiment;

FIG. 31 is a block diagram illustrating the control IC and driver ICs ina fourth embodiment of the invention;

FIG. 32 is a circuit diagram of the temperature-sensing circuit in thefourth embodiment;

FIG. 33 is a circuit diagram of a temperature-sensing circuit accordingto a fifth embodiment of the invention;

FIG. 34 is a graph illustrating the temperature characteristics of anLED;

FIG. 35 is a block diagram illustrating the control IC, driver ICs, andbandgap reference in a sixth embodiment of the invention;

FIG. 36 is a circuit diagram of the current reference circuit in thesixth embodiment;

FIG. 37 is a graph illustrating the supply-voltage dependency of thevoltage output of the temperature-sensing circuit in the firstembodiment;

FIG. 38 is a graph illustrating the supply-voltage dependency of thevoltage output of the temperature-sensing circuit in the firstembodiment as a function of the Early voltage;

FIG. 39 is a circuit diagram of a temperature-sensing circuit accordingto a seventh embodiment of the invention;

FIG. 40 is a more detailed circuit diagram of the temperature-sensingcircuit in the seventh embodiment;

FIG. 41 is a graph illustrating the supply-voltage dependency of thevoltage output signal of the temperature-sensing circuit in the seventhembodiment;

FIG. 42 is a circuit diagram of a temperature-sensing circuit accordingto an eighth embodiment of the invention;

FIG. 43 is a block diagram illustrating the control IC and driver ICs ina ninth embodiment of the invention;

FIG. 44 is a block diagram illustrating the internal structure of thedriver ICs in FIG. 43;

FIG. 45 is a circuit diagram illustrating the internal structure of oneof the driving circuits in FIG. 44, showing the circuitry for drivingone LED;

FIG. 46 is a graph illustrating test results obtained from the internalcircuit in FIG. 45 when the main driving transistor is switched on;

FIG. 47 is a graph illustrating test results obtained from the internalcircuit in FIG. 45 when the main driving transistor is switched off;

FIG. 48 is a timing diagram illustrating a first part of a testprocedure in the ninth embodiment;

FIG. 49 is a timing diagram illustrating a second part of a testprocedure in the ninth embodiment;

FIG. 50 is a sectional view of an LED head according to a tenthembodiment of the invention;

FIG. 51 is a plan view of a driver IC in the tenth embodiment;

FIG. 52 is a block diagram illustrating the printing control circuits ina conventional electrophotographic printer;

FIG. 53 is a timing diagram illustrating the operation of a conventionalelectrophotographic printer;

FIG. 54 illustrates the circuit configuration of a conventional LEDhead; and

FIG. 55 is a graph illustrating dot-to-dot and chip-to-chip variationsin an LED head.

DETAILED DESCRIPTION OF THE INVENTION

Embodiments of the invention will be described with reference to theattached illustrative drawings. As the invention relates to atemperature-sensing circuit, a driving apparatus, and a printer, thedescription will be of a printer of the invented type, having a drivingapparatus of the invented type, employing a temperature-sensing circuitof the invented type. The printer is generally similar to a conventionalprinter, having a printing control unit 1 and other units as shown inFIG. 52, but the driver ICs and control ICs in the LED head 19 differfrom the conventional ICs.

To describe control signals, the suffix -P will sometimes be added tosignal names, as in LOAD-P for example, to indicate positive logic(active high), and the suffix -N will sometimes be added, as in LOAD-Nfor example, to indicate negative logic (active low). Thus LOAD-P andLOAD-N are complementary signals, one being the inverse of the other.

Referring to FIG. 1, the first embodiment comprises a control IC 100 andtwenty-six driver ICs 101, 102, 103, . . . , 126. The control IC 100 isan integrated circuit comprising control circuitry and a non-volatilememory storing compensation data that compensate for differences in theoptical output of a plurality of LEDs. The driver ICs 101 to 126 areseparate integrated circuits that drive corresponding LED-array chips,denoted CHP1 to CHP26, each LED array chip having an array of ninety-sixLEDs for printing ninety-six dots. The driver ICs in FIG. 1 are mountedin close proximity to the corresponding LED array chips, so that athermal coupling exists between the driver ICs and the corresponding LEDarray chips. The driver ICs and LED array chips form an LED printinghead that prints lines of two thousand four hundred ninety-six dots.

    96 dots/chip×26 chips=2496 dots

The SEL input terminal of each driver IC is connected to a pull-upresistor inside the IC. The SEL input terminal of the first driver IC101 is left unconnected, and the SEL input terminal of the second driverIC 102 is coupled to the ground power-supply potential. In like manner,the SEL input terminals of all the odd-numbered driver ICs are leftunconnected, and the SEL input terminals of all the even-numbered driverICs are coupled to ground.

From the printing control unit (not visible), the control IC 100receives data signals HD-DATA₃ to HD-DATA₀, a clock signal HD-CLK, aload signal HD-LOAD, and a strobe signal HD-STB-N. The control IC 100receives these signals at terminals denoted DATA₃ to DATA₀, CLKI, LOADI,and STBI, respectively. DATA₃ to DATA₀ are input/output terminals; CLKI,LOADI, and STBI are input terminals. The control IC 100 supplies outputsignals DATAO₃ to DATAO₀, CLKO, and LOADO to input terminals DATAI₃ toDATAI₀, CLKI, and LOADI of the first driver IC 101, and supplies anoutput strobe signal STBO to input terminals STB of all of the driverICs 101 to 126.

The signals received at input terminals CLKI and LOADI of driver IC 101are coupled through internal inverting circuits to output terminals CLKOand LOADO of driver IC 101, and supplied to the CLKI and LOADI inputterminals of the next driver IC 102. These signals continue to be passedfrom one driver IC to the next, being inverted in each driver IC.

Dot driving data are input on signal lines HD-DATA₃ to HD-DATA₀. Fourbits are input at once, in synchronization with the clock signal HD-CLK,representing four adjacent dots. Input of four bits at once enables theclock rate to be reduced by a factor of four, thereby reducing thegeneration of undesired electromagnetic interference.

The data that compensate for variations in the optical output of theLEDs comprise four bits per dot, enabling the output of each LED to beadjusted in sixteen steps. These compensation data are also receivedfrom the printing control unit on signal lines HD-DATA₃ to HD-DATA₀.

The data input and output terminals DATAI₃ to DATAI₀ and DATAO₃ toDATAO₀ of the driver ICs 101 to 126 are similarly used for the input andoutput of both driving data and compensation data. The data output atoutput terminals DATAO₃ to DATAO₀ of the control IC 100 are input by thefirst driver IC 101 and shifted through the other driver ICs to the lastdriver IC 126, as described below.

Using the same input and output terminals for both driving andcompensation data has the following advantages.

First, fewer bonding wires are required for electrical interconnectionof the driver ICs to wiring traces on the printed circuit board on whichthe ICs are mounted. The assembly time of the LED head is therebyreduced.

Second, fewer wiring traces are required on the printed circuit board,so the printed circuit board and consequently the LED head can bereduced in size.

Third, there are fewer wiring traces to be inspected. A 100% inspectionof four wiring traces suffices to ensure that both driving data andcompensation data will be passed correctly from one driver IC to thenext.

FIG. 2 is a block diagram of the control IC 100, showing thenon-volatile memory and related control circuitry. The non-volatilememory is an electrically-erasable programmable read-only memory orEEPROM 100e. A clock control unit 100a supplies clock signals to theother circuits in FIG. 2, via signal lines not explicitly shown in thedrawing. A mode control unit 100b decodes and latches command signalssent to the LED head, and issues commands controlling circuitoperations. A counter 100c generates read and write addresses oninstruction from an EEPROM control unit 100d, which reads and writesdata in the EEPROM 100e.

The load signal HD-LOAD and strobe signal HD-STB-N are passed directlyfrom input terminals LOADI and STBI to output terminals LOADO and STBOof the control IC 100, without being inverted. These two signals couldbe supplied directly to the first driver IC 101 instead of being coupledthrough the control IC 100.

FIG. 3 is a block diagram showing the internal structure of the modecontrol unit 100b, which comprises a shift register 200, a decoder 201,a latch circuit 202, an inverter 203, and a counter circuit 204.

The shift register 200 has a data input terminal DI coupled to the DATA₀input/output terminal of the control IC 100. The shift register 200,latch circuit 202, and counter circuit 204 have reset terminals R thatare coupled to the load signal input terminal LOADI. The clock signalHD-CLK input at the CLKI terminal is supplied to the clock inputterminal of the counter circuit 204, and to the inverter 203. Theinverter 203 supplies an inverted clock signal to the clock inputterminal of the shift register 200. The counter circuit 204 outputs acommand latch signal to the latch circuit 202.

Data entering the shift register 200 at data input terminal DI areshifted through the shift register 200 in synchronization with the clocksignal (HD-CLK) received at input terminal CLKI. The shift register 200converts these data from serial to parallel form, and sends the paralleldata to the decoder 201 to be decoded. The decoded signals output by thedecoder 201 are latched by the latch circuit 202 in response to thecommand latch signal, and output as a direct mode signal, a write (WR)mode signal, a read (RD) mode signal, and a transfer (TRANS) modesignal. These four mode signals are active high, and only one of themcan be active at a time. When the LOADI input is inactive (low), thelatch circuit 202 is reset and the direct, write, read, and transfermode signals are all turned off.

FIG. 4 shows the input and output terminals of the EEPROM 100e. TheEEPROM 100e used in this embodiment must be able to store at least twothousand four hundred ninety-six four-bit words of data; an EEPROM witha capacity of four thousand ninety-six words, for example, may beemployed. Four-bit data are input at data input terminals DI₃ to DI₀,and output at data output terminals DO₃ to DO₀. Address signalsgenerated by the counter 100c are input at address terminals A₁₁ to A₀.A chip enable signal is input at the CE terminal. A write enable signalis input at the WE terminal.

FIG. 5 illustrates the circuits that are coupled directly to the datainput/output terminals DATA₃ to DATA₀ of the control IC 100. Each datainput/output terminal has a separate pair of buffer amplifiers 205 and206. Only one pair of buffer amplifiers is shown in the drawing.Amplifier 206 is a three-state output buffer controlled by the read (RD)mode signal. When the read mode signal is active (high), data signalsHD-DATAO₃ to HD-DATAO₀ created in the control IC 100 are output at thesedata input/output terminals DATA₃ to DATA₀. When the read mode signal isinactive (low), buffer amplifier 206 is in the high-impedance outputstate, and the external data signals on the signal lines HD-DATA₃ toHD-DATA₀ coupled to input/output terminals DATA₃ to DATA₀ are suppliedto other circuits in the control IC 100, as data signals which will bedenoted HD-DATAI₃ to HD-DATAI₀.

FIG. 6 illustrates the circuits coupled to the data output terminalsDATAO₃ to DATAO₀ of the control IC 100. Each data output terminal has aseparate two-input AND gate 210. Reference numeral 210 thus denotes fourAND gates, of which only one is visible. The other circuits in FIG. 6,namely the AND gate 212, inverter 211, and data selector 213, are singlecircuits that are shared by the four data output terminals.

All four AND gates 210 have the transfer mode signal (TRANS) as one oftheir two inputs. The other inputs to these AND gates 210 are thelatched data outputs from the EEPROM 100e, which are held in latches notexplicitly shown in the drawings, and are denoted LATCH-DO₃ toLATCH-DO₀. The four outputs of the AND gates 210 are supplied to fourdata input terminals of the data selector 213, collectively denoted bythe letter B in FIG. 6.

The data selector 213 has four more data input terminals, collectivelydenoted by the letter A, that receive the data signals HD-DATAI₃ toHD-DATAI₀ shown in FIG. 5. The data selector 213 selects the A datainputs when the input at the select (S) input terminal is low, selectsthe B data inputs when the S input is high, and outputs the selecteddata from the DATAO₃ to DATAO₀ output terminals to the first driver IC101.

The S input is created by AND gate 212 from the LOADI input and thedirect mode signal, the latter being inverted by inverter 211. Thus whenthe LOADI input is inactive (low), or when the direct mode signal isactive (high), S is low and HD-DATAI₃ to HD-DATAI₀ are output at DATAO₃to DATAO₀. When the transfer mode signal and LOADI signals are bothactive (high), the latched EEPROM output data LATCH-DO₃ to LATCH-DO₀ areoutput at DATAO₃ to DATAO₀.(When the transfer mode signal is high, thedirect mode signal is automatically low.)

FIG. 7 illustrates the clock control unit 100a, which comprises buffercircuits 215 and 219, an inverter 216, a three-input OR gate 217, and anAND gate 218. Buffers 215 and 219 couple the STBI and LOADI inputterminals to the STBO and LOADO output terminals. The other circuitelements are coupled so as to transmit the HD-CLK signal from the CLKIinput terminal to the CLKO output terminals when the transfer or directmode signal is active (high), or when LOADI is low.

FIG. 8 illustrates the internal structure of the counter 100c thatgenerates address signals for the EEPROM 100e. This counter comprises aflip-flop circuit 221 having a set (S) input terminal, a clock selector222, another flip-flop circuit 223, a latch circuit 224, and a countercircuit 225.

Flip-flop circuits 221 and 223 both operate as toggle flip-flops,dividing the frequency of the HD-CLK signal input at CLKI by two. Theoutputs of these flip-flop circuits are a write enable signal (WE-N) anda second clock signal CLK2. The second clock signal CLK2 is input to thelatch circuit 224, which latches data signals HD-DATAI₃ to HD-DATAI₀ andsupplies these signals to the data input terminals DI₃ to DI₀ of theEEPROM 100e.

When the write (WR) mode signal is active (high), clock selector 222selects CLK2 for input to the counter circuit 225, which generatessuccessive addresses at the address input terminals A₁₁ to A₀ of theEEPROM 100e. The write enable signal WE-N cycles between the active andinactive states in synchronization with the CLKI input. These operationscause the input data HD-DATAI₃ to HD-DATAI₀ to be written into theEEPROM 100e in synchronization with CLK2.

When the write mode signal is inactive, the write enable signal WE-N isheld in the inactive state, so the data inputs to the EEPROM 100e areignored. In addition, clock selector 222 selects the HD-CLK signal inputat the CLKI terminal, so the counter circuit 225 generates one addressper HD-CLK cycle. These addresses are used for reading data from theEEPROM 100e in synchronization with HD-CLK.

FIG. 9 is a timing diagram illustrating the sending of a modedesignation command to the LED head on the HD-DATA₀ signal line. Beforethe command is sent, the HD-LOAD signal is driven high to release themode-setting circuit from the reset state. Next, serial data comprisingbits d₃, d₂, d₁, and d₀ are input on the HD-DATA₀ signal line, insynchronization with the HD-CLK signal.

At the fifth HD-CLK cycle, the counter circuit 204 in FIG. 3 activatesthe command latch signal, causing the latch circuit 202 to latch themode signals decoded from data d₃, d₂, d₁, and d₀ by the decoder 201,thereby setting the mode. This mode setting remains latched until theHD-LOAD signal goes low again. Next, further HD-CLK cycles aregenerated, causing the logic circuits in the LED head to operateaccording to the selected mode.

FIG. 10 lists the command data assignments to bits d₃, d₂, d₁, and d₀.The four operating modes in this embodiment can be described as follows.

In the write mode, compensation data derived from measurements of theoptical output of the LEDs are written into the EEPROM 100e. This modeis used for writing compensation data into the EEPROM 100e when the LEDhead is manufactured.

In the transfer mode, the compensation data stored in the EEPROM 100eare read out and transferred to the driver ICs. This mode is used when,for example, the printer is powered up during normal use.

In the direct mode, compensation data derived from measurements of theoptical output of the LEDs are transferred directly to the driver ICs,without being stored in the EEPROM 100e. Direct transfer enables themanufacturer to test the effect of compensation data before writing thecompensation data into the EEPROM 100e. Direct transfer is quicker thanfirst writing the data in the EEPROM, then transferring the data in thetransfer mode.

In the read mode, the data stored in the EEPROM 100e are read out andprovided from input/output terminals DATA₃ to DATA₀ to an externaldevice, through a connector attached to the LED head. Read mode isuseful in testing the LED head and confirming that the correctcompensation data have been stored.

FIG. 11 is a timing diagram of the operation of sending the read modecommand, then reading data from the EEPROM 100e. After the read modecommand `1000` has been sent, the printing control unit places HD-DATA₃to HD-DATA₀ in the high-impedance state, during the interval marked A inthe drawing, and outputs a fifth HD-CLK pulse. At the trailing edge ofthis fifth HD-CLK pulse, the read mode is set and input/output terminalsDATA₃ to DATA₀ are placed in the output state by activating the bufferamplifiers 206 shown in FIG. 5. These terminals remain in the outputstate until the HD-LOAD signal goes low to terminate the read mode, atthe point marked B in the drawing. During the read mode, the EEPROMaddress changes at each HD-CLK cycle, and the data stored at theseEEPROM addresses are latched and output on the HD-DATA₃ to HD-DATA₀signal lines as DATA₀, . . . , DATA_(n), DATA_(n+1), . . . .

FIG. 12 is a more detailed timing diagram showing how data are read outof the EEPROM. Successive addresses ADR_(n), ADR_(n+1), ADR_(n+2) aresent to the address terminals A₁₁ to A₀. The data (DATA_(n+1)) stored ataddress ADR_(n+1) are output from terminals DO₃ to DO₀ of the EEPROM,and latched by a latch circuit in synchronization with a latch clocksignal (LATCH CLK) output from the clock control unit 100a (this latchcircuit and latch clock signal were not explicitly shown in thepreceding drawings). The latched data become the signals LATCH-DO₃ toLATCH-DO₀ supplied to the circuit in FIG. 6. In read mode, the latcheddata also become the signals HD-DATAO₃ to HD-DATAO₀ which are outputfrom data input/output terminals DATA₃ to DATA₀ as shown in FIG. 5.

FIG. 13 is a timing diagram illustrating the operation of writing datainto the EEPROM. After the write mode has been selected by serialcommand data sent to the LED head, further HD-CLK cycles cause the dataon signal lines HD-DATA₃ to HD-DATA₀ to be written into the EEPROM insynchronization with the CLK2 signal, which has half the frequency ofthe HD-CLK signal. CLK2 is selected by the clock selector 222 in FIG. 8.Successive addresses ADR_(n), ADR_(n+1), ADR_(n+2) are generated bycounting CLK2, and furnished to the address terminals A₁₁ to A₀. Theexternally supplied data HD-DATA₃ to HD-DATA₀ become HD-DATAI₃ toHD-DATAI₀, which are latched in synchronization with CLK2, producing thedata series DATA_(n), DATA_(n+1), DATA_(n+2) in FIG. 13. These data aresupplied to the input terminals DI₃ to DI₀ of the EEPROM, and latchedinside the EEPROM at low-to-high transitions of the WE-N signal.

After thirty-two WE-N cycles, the latched data are written into theEEPROM memory cells. Due to the properties of the memory cells, eachdata write takes about ten milliseconds (10 ms). The printing controlunit halts HD-CLK input while the write is in progress. After 10 ms,data input and HD-CLK input resume for thirty-two more WE-N cycles, thenHD-CLK is halted again while the next thirty-two four-bit data words arewritten in the EEPROM memory cells. The write operation continues torepeat in this way.

FIG. 14 is a block diagram of the first driver IC 101 in FIG. 1. All ofthe circuits enclosed in the dotted line are integrated into this driverIC. Driver ICs 102 to 126 have similar configurations. The main elementsare a shift register 230a for transferring driving data and compensationdata, a group of latch circuits 230b for temporarily latching thetransferred driving data, a group of compensation memory circuits 230cfor storing the transferred compensation data, and a group of drivingcircuits 230d for feeding current to LEDs designated by the drivingdata, in amounts adjusted according to the compensation data.

Each driver IC also has input buffer circuits 231 to 234, output buffercircuits 235 to 238, inverters 239, 241, 242, 245, and 246, exclusive-ORgates 240 and 244, a pull-up resistor 243, and a current referencecircuit 247. The input buffer circuits 231 to 234 couple input terminalsDATAI₃ to DATAI₀ to input terminals S/R-I₃ to S/R-I₀ of the shiftregister 230a. The output buffer circuits 235 to 238 couple outputterminals DATAO₃ to DATAO₀ to output terminals S/R-O₃ to S/R-O₀ of theshift register 230a.

The clock signal input to driver IC 101 at the CLKI terminal is invertedby inverter 239 and output at the CLKO output terminal. The load signalinput at the LOADI terminal is inverted by inverter 242 and output atthe LOADO output terminal. The signals output at output terminals CLKOand LOADO are supplied to the next driver IC 102. These signals continueto be passed from one driver IC to the next driver IC until they reachthe last driver IC 126.

Since the above signals are inverted by the inverters 239 and 242 asthey pass through each driver IC, even if there are differences betweenthe rise time and fall time of the inverters, these differences will beaveraged out as the signals pass through the driver ICs, and the pulsewidth of the signals input to the CLKI and LOADI terminals of driver IC126 will be substantially the same as the pulse width of the signalsinput to the CLKI and LOADI terminals of driver IC 101.

If the SEL input terminal is left unconnected, as in driver IC 101,pull-up resistor 243 generates a high signal, so that the S/R-CLK andLOAD-P signals are logically equivalent to the signals input at the CLKIand LOADI terminals. If the SEL input terminal is grounded, as in driverIC 102, then S/R-CLK and LOAD-P are logically inverted with respect tothe CLKI and LOADI inputs; consequently, S/R-CLK and LOAD-P in all ofthe driver ICs 101 to 126 are logically equivalent to the CLKI and LOADIinputs to driver IC 101.

FIG. 15 illustrates the interconnections between the shift register 230aand the group of latch circuits 230b. FIG. 16 illustrates theinterconnections among the shift register 230a and the groups of latchcircuits 230b, compensation memory circuits 230c, driving circuits 230d,and the driven LEDs. The group of compensation memory circuits 230ccomprises the compensation memory circuits CM1a, CM1b, . . . shown inFIG. 16. FIG. 16 shows only the initial portion of the shift register230a, group of latch circuits 230b, group of compensation memorycircuits 230c, and group of driving circuits 230d, but the remainingportion of the circuit configuration is similar to this initial portion.

The shift register 230a has twenty-four stages, through which drivingdata and compensation data are shifted in four-bit parallel form. Thefirst stage comprises four flip-flop circuits 301a, 301b, 301c, and301d; the second stage comprises four flip-flop circuits 302a, 302b,302c, and 302d; the last stage comprises four flip-flop circuits 324a,324b, 324c, and 324d. The clock signal S/R-CLK is supplied to the clockterminals of the flip-flop circuits in FIGS. 15 and 16. The data outputfrom the flip-flop circuits 301a, 301b, . . . in the shift register 230aare denoted S/R-DOT1, S/R-DOT2, . . . , while the corresponding dataoutput from the latch circuits are denoted LATCH-DOT1, LATCH-DOT2, . . ., as indicated in FIG. 15.

The group of latch circuits 230b comprises latch elements 401a to 424dthat receive and temporarily store the outputs of the correspondingflip-flop circuits 301a to 324d in the shift register 230a. The fourlatch elements that receive and store the outputs of the four flip-flopcircuits in the same shift-register stage constitute what will bereferred to below as one latch circuit. For example, the fourfirst-stage latch elements 401a to 401d constitute one latch circuit401.

The group of compensation memory circuits 230c has compensation memorycircuits CM1a to CM24d that receive and store the outputs of thecorresponding flip-flop circuits 301a to 324d in the shift register230a. Each compensation memory circuit has four memory cells, denotedc0, c1, c2, and c3, and stores four bits of data. The signals denotedbit₀ -WR to bit₃ -WR that determine which memory cell receives each databit are generated by circuits that will be shown in FIGS. 22 to 24.

The group of driving circuits 230d comprises driving circuits (DRC) thatreceive the outputs of flip-flop circuits 301a to 324d, latch elements401a to 424d, and compensation memory circuits CM1a-CM24d, and supplydrive current through corresponding output terminals to the LEDs in thecorresponding LED array chip (CHP). Each LED is driven by a separatedriving circuit.

The compensation data are written into the compensation memory circuits230c when the LED head is powered up, remain stored in those memorycircuits until power is switched off, and are used repeatedly duringprinting. During the writing of compensation data at power-up, the shiftregister 230a transfers data supplied from the EEPROM 100e in thecontrol IC 100. During the printing of data, the shift register 230atransfers driving data supplied from the printing control unit. Thedriving data are latched by the latch circuits 401 to 424. Thecompensation data bypass the latch circuits 401 to 424.

As can be seen from FIGS. 1 and 14, the shift registers 230a in driverICs 101 to 126 are interconnected to form one continuous shift register,which functions as a four-bit parallel data transfer means. Due to theadoption of parallel transfer, a typical bit need be shifted throughonly twenty-four of the ninety-six flip-flop circuits in each driver IC.For example, the bit input at input terminal S/R-I₀ in FIGS. 15 and 16is shifted through flip-flops 301a, 302a, . . . , 324a.

During the transfer and writing of compensation data, four bits aretransferred for each LED. The transfer and writing of these bits takeplace in the following sequence.

First, the most significant bits (bit b₃) of compensation data for allthe LEDs are shifted through the shift registers 230a in the driver ICsuntil each of the flip-flops 301a to 324d in each driver IC holds onemost significant bit; then these most significant bits are all writtenat once into the first memory cell (c3) in each compensation memorycircuit.

Next, the second bits (bit b₂) of compensation data for all the LEDs aresimilarly shifted through the shift registers 230a in the driver ICs andall written at once into the second memory cells (c2) in thecompensation memory circuits.

Following this, the third bits (bit b₁) of compensation data for all theLEDs are likewise shifted through the shift registers 230a in the driverICs and all written at once into the third memory cells (c1) in thecompensation memory circuits.

Finally, the fourth bits (bit b₀) of compensation data for all the LEDsare shifted through the shift registers 230a in the driver ICs and allwritten at once into the fourth memory cells (c0) in the compensationmemory circuits.

In the transfer of driving data during printing, only one bit per LED istransferred. After all bits have been transferred into the flip-flops301a to 324d of the shift registers, all bits are latched simultaneouslyby the latch elements 401a to 424d in the latch circuits. The drivingdata held in the latch circuits and the compensation data stored in thecompensation memory circuits are then transferred to the correspondingdrive circuits (DRC) and used in driving the LEDs.

The compensation memory circuits have static memory cells. The fourmemory cells in each memory circuit share a common input line, which iscoupled to the corresponding flip-flop in the shift register 230a.

FIG. 17 illustrates the latch circuits 401 to 424. The LOAD-P signal issupplied to the enable (G) input terminals of all latch elements from401a to 424d. Data received at the input terminals (D) of these latchelements are reproduced at their output terminals (Q), but the outputdata (Q) cannot change while LOAD-P is low.

FIG. 18 illustrates the detailed circuit configuration of thecompensation memory circuits. Only the compensation memory circuits CM1aand CM1b pertaining to the first two LEDs are shown, but the othercompensation memory circuits are similar.

Each of the compensation memory circuits separately has inverters 451 to459, n-channel MOS transistors 471 to 478, read-out signal lines forbits b₀ to b₃, and a buffer 491. The buffers 491 receive the dataS/R-DOT1, S/R-DOT2, . . . output by the shift register 230a.

Inverters 451 and 452 store bit b₀ of the LED compensation data. Writingof bit b₀ is controlled by n-channel MOS transistors 471 and 472. Thegates of these transistors 471 and 472 receive the write command signalbit₀ -WR. The other bits (b₁, b₂, b₃) are stored in similar fashion inthe other pairs of inverters.

Inverters 451 and 452 and transistors 471 and 472 constitute memory cellc0 in FIG. 16. Similarly, inverters 453 and 454 and transistors 473 and474 constitute memory cell c1, inverters 455 and 456 and transistors 475and 476 constitute memory cell c2, and inverters 457 and 458 andtransistors 477 and 478 constitute memory cell c3.

The memory cell that stores one bit of compensation data comprises twoMOS transistors and two inverters. Each inverter comprises two MOStransistors. Six transistors thus suffice to store each bit ofcompensation data, instead of the twenty transistors that would berequired if flip-flop circuits were employed for the storage ofcompensation data. This makes the circuit size of the present embodimentmuch smaller than the size of a driver IC storing compensation data inflip-flop circuits.

The memory cells in FIG. 18 are similar to well-known staticrandom-access memory (SRAM) cells, but with one significant difference.In an SRAM, data are read out from the memory cells onto a common bus,so the number of bits that can be read simultaneously is limited by thebus width. In FIG. 18, however, each memory cell has its own read-outsignal line, so all of the nearly ten thousand bits of compensation datastored in the compensation memory circuits in the LED head aresimultaneously readable.

FIG. 19 illustrates the internal structure of the current referencecircuit 247, which comprises an operational amplifier 501, a p-channelMOS transistor 502, and a resistor with a resistance value of R_(ref).The function of this circuit is to generate a control voltageV_(control) for use in the driving circuits.

The inverting (-) input terminal of the operational amplifier 501receives a reference voltage V_(ref) output from a temperature-sensingcircuit that will be described later (FIG. 27). The non-inverting (+)input terminal of operational amplifier 501 is coupled through p-channelMOS transistor 502 to the power supply (V_(DD)), and through resistorR_(ref) to ground. The transistor 502 and resistor R_(ref) are thuscoupled in series between V_(DD) and ground. The output of theoperational amplifier 501, which is the control voltage V_(control), isapplied to the gate of the p-channel MOS transistor 502. The operationalamplifier 501 operates so as to equalize the inputs at its two inputterminals. This operation produces a constant reference current I_(ref)through transistor 502 and resistor R_(ref), given by the followingequation:

    I.sub.ref =V.sub.ref /R.sub.ref

FIG. 20 illustrates one of the driving circuits in the group of drivingcircuits 230d, and the output terminal 525 through which this drivingcircuit drives one LED (the n-th LED in the LED array). The anode of theLED (not visible) is coupled to output terminal 525.

The circuit in FIG. 20 comprises AND gates 504 to 508, a buffer circuit509, p-channel MOS transistors 510 to 514, n-channel MOS transistors 515to 519, and p-channel MOS transistors 520 to 524 that feed drive currentto output terminal 525.

The inputs to AND gate 504 are the LATCH-DOTn signal and an LED-DRV-ONsignal. The output terminal of AND gate 504 is coupled to inputterminals of AND gates 505 to 508 and buffer circuit 509. The otherinput terminals of AND gates 505 to 508 receive compensation data bitsb₃ to b₀, respectively, from the corresponding compensation memorycircuit, as shown in FIG. 18. The source terminals of n-channel MOStransistors 515 to 519 receive the control voltage V_(control) output bythe current reference circuit 247 in FIG. 19.

Transistor 524 is the main driving transistor that feeds driving currentto the LED. Transistors 520 to 523 are compensation transistors thatfeed additional current to adjust the optical output of the LED.Transistors 520 to 523 have equal gate lengths, and their gate widthsare in the ratio 8:4:2:1, corresponding to compensation data bits b₃ tob₀. (Transistors 502 and 520 to 524 all have the same gate length.)Transistors 520 to 523 generate weighted compensation currents inproportion to their gate widths.

Transistor 524 is switched on when the LED-DRV-ON and LATCH-DOTn signalsare both high. Transistors 520 to 523 are switched on when LED-DRV-ON,LATCH-DOTn, and the corresponding compensation data bits b₃ to b₀ areall high. The current supplied from output terminal 525 to the LED isthe sum of a main driving current contributed by transistor 524, andweighted compensation currents contributed by those transistors 520 to523 that are switched on.

Transistors 510 to 519 form five inverters through which the gates oftransistors 520 to 524 are driven. The control voltage V_(control)output by the current reference circuit 247 is supplied to the sourceterminals of transistors 515 to 519. When transistors 515 to 519 areswitched on, they supply voltages substantially equal to V_(control) tothe gate terminals of the driving transistors 520 to 524. Transistor 502in FIG. 19 and transistors 520 to 524 in FIG. 20 thus form a currentmirror.

The drain currents output by driving transistors 520 to 524 (whenswitched on) are determined by the ratios of the gate widths of thesedriving transistors to the gate width of transistor 502. The LED drivingcurrents supplied by the driving transistors 520 to 524 in all of thedriving circuits 230d in the driver IC are controlled simultaneously bythe control voltage V_(control), which in turn is controlled by thereference voltage V_(ref) output by the temperature-sensing circuit tobe described below. Specifically, the driving currents are proportionalto the reference current I_(ref) in FIG. 19, which is proportional tothe reference voltage V_(ref).

The bar graph in FIG. 21 illustrates the relative sizes of the currentsoutput by p-channel MOS transistors 520, 521, 522, 523, and 524 whenthese transistors are driven. The main driving current has a value I₀.The compensation currents output in response to bits b₃, b₂, b₁, and b₀have values of 8ΔI, 4Δ1, 2ΔI, and ΔI, respectively. The quantity ΔIrepresents the minimum step in which the LED driving current can bevaried by the compensation data. By storing various compensation datavalues, the LED driving current can be varied in sixteen steps, rangingfrom I₀ (when b₃, b₂, b₁, and b₀ are all zero) to I₀ +15ΔI (when b₃, b₂,b₁, and b₀ are all one).

FIG. 22 illustrates a timing generator (not shown in FIG. 14) which isdisposed in driver ICs 101 to 126. The timing generator comprises a pairof flip-flop circuits 531 and 532 and a NOR gate 533, which areinterconnected to form a ring counter. The LOAD-P signal is supplied tothe reset input terminals of flip-flop circuits 531 and 532. The STB-Psignal is supplied to the clock input terminals of flip-flop circuits531 and 532. The outputs of this timing generator are a bit select clock(BIT SEL CLK) signal and a write trigger (WR-TRIG) signal. For everythree cycles of STB-P, one BIT SEL CLK pulse is output, followed by oneWR-TRIG pulse, as will be shown in FIG. 26.

FIG. 23 illustrates a compensation bit position counter (not shown inFIG. 14) which is disposed in the driver ICs. This counter comprisesflip-flop circuits 534 and 535, which are interconnected to form aJohnson counter. The LOAD-P signal is supplied to the reset inputterminals of flip-flop circuits 534 and 535. The BIT SEL CLK signal issupplied to the clock input terminals of these flip-flop circuits 534and 535. The outputs of this counter are two complementary pairs ofsignals denoted Q1-P, Q1-N, Q2-P, and Q2-N.

FIG. 24 illustrates a word-line decoder (also not shown in FIG. 14)which is disposed in each of the driver ICs. This decoder comprises NANDgates 536 to 539 and inverters 540 to 543. All four NAND gates 536 to539 receive the WR-TRIG signal output by the timing generator in FIG.22. Each NAND gate also receives two of the signals Q1-P, Q1-N, Q2-P,and Q2-N output by the compensation bit position counter. The outputs ofthe NAND gates go low one at a time responsive to different combinationsof the logic levels of Q1-P, Q1-N, Q2-P, and Q2-N. These outputs areinverted by inverters 540 to 543 to generate the signals bit₃ -WR tobit₀ -WR that control the writing of compensation data into thecompensation memory circuits.

The word-line decoder circuit also generates the LED-DRV-ON signal bymeans of an AND gate 544 that receives the STB-P and LOAD-N signals.When the load signal is active (when LOAD-P is high and LOAD-N is low),LED-DRV-ON is held in the inactive (low) state, so that the LEDs are notdriven.

The circuits in FIGS. 23 and 24 combine to activate bit₃ -WR, bit₂ -WR,bit₁ -WR, and bit₀ -WR in turn at four consecutive BIT SEL CLK pulses.

FIG. 25 illustrates the operation of transferring the compensation datainto the compensation memory circuits of driver ICs 101 to 126. Thisoperation is performed when the LED head is powered up, or at some othersuitable time before printing begins, and is controlled by the printingcontrol unit or a higher-order controller (not shown in the drawings).The compensation data are read from the EEPROM 100e in the control IC100.

Signals HD-LOAD, HD-DATA₃ to HD-DATA₀, HD-CLK, and HD-STB-N in FIG. 25are provided from the printing control unit to the LED head through aconnector attached to the LED head. Signals DATAO₃ to DATAO₀ and CLKOare supplied from the control IC 100 to driver IC 101 in FIG. 1. TheDATA-WR signal collectively indicates the four signals bit₃ -WR to bit₀-WR shown in FIGS. 16, 18, and 24, which are generated in each of thedriver ICs.

The operation begins when the HD-LOAD signal goes high as shown at thetop left (a) in FIG. 25. Next, command data are transferred on theHD-DATA₀ signal line in synchronization with HD-CLK (A). The commanddata (`0100`) specify the transfer (TRANS) command, as shown in FIG. 10,which instructs the control IC 100 to transfer compensation data fromits internal EEPROM to the driver ICs.

When the command data have been transferred and the control IC 100 hasbeen placed in the transfer mode, further HD-CLK cycles are generated totransfer the compensation data. First, the most significant bits (b₃),comprising one bit for each LED, are read from the EEPROM andtransferred into the shift registers 230a of the driver ICs. After thenumber of HD-CLK cycles (B) necessary to transfer all of the mostsignificant bits, HD-CLK is temporarily halted and three HD-STB-N pulsesare produced (C).

From these HD-STB-N pulses, each driver IC generates the write commandsignal b₃ -WR needed to write the transferred bits into the compensationmemory circuits (D). The notation bit₃ -WR in FIG. 25 indicates that atthis point in the drawing, DATA-WR represents bit₃ -WR. The bit₃ -WRsignals cause all of the data held in the shift registers 230a in thedriver ICs to be written into memory cells c3 (FIG. 16) of thecompensation memory circuits and stored by inverters 457 and 458 (FIG.18).

Next, the printing control unit sends further HD-CLK cycles to transferthe next bits (b₂) of compensation data (E), followed by three moreHD-STB-N pulses (F), which cause the driver ICs to generate bit₂ -WRsignals (G). These bits (b₂) are thereby written into memory cells c2(FIG. 16) in the compensation memory circuits, and stored by inverters455 and 456 in FIG. 18.

In the same way the third bits (b₁) are transferred to the driver ICsand written in their compensation memory circuits (H, I, J). Then thelast bits (b₀) are similarly transferred and written (K, L, M). At thispoint four bits of compensation data (b₃, b₂, b₁, and b₀) have beenstored sequentially in the memory cells c3, c2, c1, and c0 in eachcompensation memory circuit.

Finally, the HD-LOAD signal is driven low (b) to end the transfer ofcompensation data and prepare for the transfer of driving data. Theoperation illustrated in FIG. 25 thus comprises a command transfer phase(A), followed by four compensation data transfer cycles (B-C-D, E-F-G,H-I-J, and K-L-M), with each compensation memory circuit receiving onebit of compensation data per cycle.

The timing diagram in FIG. 26 illustrates the operation of the timinggenerator (FIG. 22), compensation bit position counter (FIG. 23), andword-line decoder (FIG. 24) during the writing of data into thecompensation memory circuits. The letters C, D, F, G, I, J, L, and M inFIG. 26 have the same meaning as in FIG. 25.

The HD-STB-N signal output from the printing control unit is buffered inthe control IC 100 and received at the STB input terminals of all thedriver ICs (FIG. 1). In each driver IC, inverter 246 (FIG. 14) invertsthe STB input to produce STB-P, which clocks the ring counter comprisingflip-flop circuits 531 and 532 in FIG. 22. LOAD-P is high, so theseflip-flop circuits 531 and 532 are not reset.

The first rising edge of STB-P in FIG. 26 (C) causes BIT SEL CLK to gohigh. The second rising edge of STB-P causes BIT SEL CLK to go low andWR-TRIG to go high. The third rising edge of STB-P causes WR-TRIG to golow. The same sequence occurs at the other groups of strobe pulses (F,I, L).

Signals Q1-P and Q2-P are generated by the circuit in FIG. 23, in whichflip-flop circuits 534 and 535 form a Johnson counter clocked by BIT SELCLK. The four rising edges of BIT SEL CLK in FIG. 26 cause Q1-P and Q2-Pto assume, in turn, the four pairs of values `10,` `11,` `01,` and `00.`The word-line decoder in FIG. 24 decodes these pairs of values and theWR-TRIG signal to generate signals bit₃ -WR to bit₀ -WR (shown at D, G,J, and M).

When the load signal is active (when LOAD-P is high and LOAD-N is low),AND gate 544 in FIG. 24 disables the LED-DRV-ON signal, so that theSTB-P pulses in FIG. 26 do not cause LED-DRV-ON to go high.

During printing, LED-DRV-ON output is enabled. The load signal isinactive (LOAD-N is high and LOAD-P is low) when STB-P goes high, soSTB-P propagates through AND gate 544 to become the LED-DRV-ON signal.Printing is carried out with the same signal timing sequence as in theprior art, illustrated in FIG. 53.

FIG. 27 shows the temperature-sensing circuit that generates thereference voltage V_(ref) used in the current reference circuit 247,comprising npn bipolar transistors Q₁ and Q₂, p-channel MOS transistorsM₁, M₂, and M₃, and resistors R₀, R₁, and R₃. Transistors Q₁ and Q₂differ in size; transistor Q₂ may be several times larger thantransistor Q₁. The size ratio Q₁ :Q₂ will be denoted 1:K below.Transistors M₁, M₂, and M₃ have mutually equal dimensions, that is,mutually equal gate widths and mutually equal gate lengths. Resistors R₀and R₃ are of identical type: for example, both are polysiliconresistors, or both are diffused resistors.

The source terminals of transistors M₁, M₂, and M₃ are coupled in commonto the power supply V_(DD). The gate terminals of transistors M₁, M₂,and M₃ are connected in common to the drain terminal of transistor M₂.In this configuration, transistors M₁, M₂, and M₃ operate as a currentmirror circuit 580, supplying substantially equal drain currents I₁, I₂,and I₃ determined by their common gate-source voltage.

Resistors R₁ and R₀ and npn bipolar transistor Q₁ are coupled in seriesbetween the drain terminal of MOS transistor M₁ and ground. That is, afirst terminal of resistor R₁ is coupled to the drain terminal oftransistor M₁, a second terminal of resistor R₁ is coupled to a firstterminal of resistor R₀, a second terminal of resistor R₀ is coupled tothe collector terminal (C) of transistor Q₁, and the emitter terminal(E) of transistor Q₁ is coupled to ground. The base terminal (B) oftransistor Q₁ is coupled to a point between resistors R₁ and R₀.

The collector terminal of transistor Q₂ is coupled to the drain terminalof MOS transistor M₂, making the drain current I₂ of transistor M₂ equalto the collector current of transistor Q₂. The emitter terminal oftransistor Q₂ is coupled to ground. The base terminal of transistor Q₂is coupled to a point between resistor R₀ and the collector terminal oftransistor Q₁.

The drain current I₁ of MOS transistor M₁ flows through resistors R₁ andR₀ to the collector of transistor Q₁, then from the emitter oftransistor Q₁ to ground. Part of this current I₁, also flows into thebase terminals of bipolar transistors Q₁ and Q₂, but the current gainsof transistors Q₁ and Q₂ are sufficiently large that their base currentsare negligible in comparison with their collector currents. I₁ istherefore substantially equal to the collector current of transistor Q₁.

The drain terminal of MOS transistor M₃ is coupled through resistor R₃to ground, and is also coupled to the inverting input terminal of theoperational amplifier 501 in the current reference circuit 247, shown inFIG. 19. Resistor R₃ operates as a converting element, converting thedrain current I₃ output by MOS transistor M₃ in the current mirrorcircuit 580 to the reference voltage V_(ref) used by the currentreference circuit 247.

Since the base current of transistor Q₁ is negligible, its emittercurrent is substantially equal to the collector current I₁. The emittercurrent (I₁) is described by the following equation, in which V_(BE1) isthe base-emitter voltage of transistor Q₁, I_(S) is the saturationcurrent of transistor Q₁, k is the Boltzmann constant, q is the chargeof the electron, T is the absolute temperature of transistor Q₁, and expis the exponential function.

    I.sub.1 =I.sub.S exp(qV.sub.BE1 /kT)

Rearranging and taking natural logarithms (ln) gives the followingexpression for V_(BE1).

    V.sub.BE1 =(kT/q)ln(I.sub.1 /I.sub.S)

A similar relationship holds for the base-emitter voltage V_(BE2) oftransistor Q₂. The saturation current of transistor Q₂ is KI_(S), so therelationship is as follows.

    V.sub.BE2 =(kT/q)ln(I.sub.2 /KI.sub.S)

The difference ΔV_(BE) between the base-emitter voltages of transistorsQ₁ and Q₂ is accordingly the following. ##EQU1##

Since I.sub. and I₂ are substantially equal, this relationship can beapproximated as follows.

    ΔV.sub.BE =(kT/q)ln(K)

Since ΔV_(BE) is also the voltage across resistor R₀, current I₁ can beexpressed as follows. ##EQU2##

Bipolar transistor Q₂ produces a transistor output signal, namely acollector voltage signal, that controls the currents supplied by thecurrent mirror circuit 580, because it is also the gate voltage of MOStransistors M₁, M₂, and M₃. One of these currents (I₁) determines thebase-emitter voltages of bipolar transistors Q₁ and Q₂. The equationsabove show that the currents supplied by the current mirror circuit 580are proportional to the absolute temperature T of transistors Q₁ and Q₂.

The reference voltage V_(ref) can be expressed as follows. ##EQU3##

Since resistors R₀ and R₃ are of the same type, they have identicaltemperature coefficients. The reference voltage V_(ref) is thereforealso proportional to the absolute temperature T.

The temperature coefficient of V_(ref) is defined to be the followingquantity.

    (1/V.sub.ref)(V.sub.ref /T)

With this definition, the temperature coefficient is inverselyproportional to T.

    (1/V.sub.ref)(V.sub.ref /T)=1/T

At room-temperature conditions in the vicinity of three hundred kelvins(300 K), the temperature coefficient is approximately 0.33%/° C.

The above argument does not require I₁, I₂ and I₃ to be equal;essentially the same conclusion is reached if they are related by fixedproportionality factors.

As explained above, the operational amplifier 501 operates to make theLED driving current proportional to the reference voltage V_(ref). Thetemperature-sensing circuit in FIG. 27 accordingly makes the LED drivingcurrent proportional to the absolute temperature T of bipolartransistors Q₁ and Q₂. Due to the thermal coupling between the LED arraychip and its driver IC, the temperature T of bipolar transistors Q₁ andQ₂ varies together with the temperature of the LED array chip. Thus asthe temperature of an LED array chip rises, the driving current suppliedto the LEDs in that LED array chip increases to compensate for thereduced optical output efficiency of the LEDs.

To obtain a reference voltage V_(ref) of 1.5 V at a typical roomtemperature of 25° C., the transistor size ratio can be set equal to ten(K=10), the resistance R₀ to 10 kΩ, and the resistance R₃ to 254 kΩ. Thereference voltage at 85° C. will then be 1.8 V.

As is clear from the preceding description, during the operation of theprinter, the temperature-sensing circuit in each driver IC senses thetemperature of the driver IC, which corresponds to the temperature ofthe driven LED array chip, and generates a corresponding referencevoltage V_(ref). The current reference circuit 247 shown in FIG. 19operates as a temperature compensation circuit, using the referencevoltage V_(ref) to compensate for temperature-induced variations in theoptical output of the LEDs. Printing irregularities due to temperaturedifferences between the LED array chips can thus be reduced.

The advantages of the first embodiment can be summarized as follows.

When compensation data are transferred from the control IC 100 to thedriver ICs according to the first embodiment, the compensation data aretransferred by the same shift registers that are also used fortransferring driving data during printing, and the compensation dataheld in the shift registers are stored simultaneously in thecompensation memory circuits in the driver ICs. Compared with the use ofa separate shift register comprising flip-flop circuits to transfer andstore the compensation data, the present embodiment requires fewertransistors, fewer external terminals, and fewer wire-bondinginterconnections, thereby reducing the size and cost of the driver ICs.Assembly and testing costs are also reduced. In particular, the testingof logic functions in the LED head and inspection of wire-bondinginterconnections are simplified.

The LOAD-P signal distinguishes between the transfer of compensationdata and the transfer of driving data. When LOAD-P is high, the STB-Psignal does not strobe the LEDs, so STB-P can be used to generate writecontrol signals for the memory cells. Moreover, the driver ICsinternally generate the write command signals that determine whichmemory cells receive which bits of compensation data. Thus the firstembodiment can be practiced without the need for additional signalterminals in the LED head.

When the LED head is manufactured, the LEDs are driven one by one atroom temperature, their optical outputs are measured, and compensationdata are stored in the EEPROM 100e in the control IC 100 so that underuniform temperature conditions, all LEDs will emit substantially equaloptical power. Under actual printing conditions, if some LED array chipsare driven more heavily than others and generate more heat, part of thisheat is conducted to the adjacent driver ICs. The temperature of eachdriver IC corresponds closely to the temperature of the driven LED arraychip. As the LED array chips and driver ICs are made of materials withhigh thermal conductivity, temperature differences within each chip orIC are slight. By sensing the temperature at a single point within adriver IC and adjusting the driving current supplied to the driven LEDarray chip according to the temperature at this point, thetemperature-sensing circuit in FIG. 27 and temperature compensationcircuit in FIG. 19 can markedly reduce the optical output irregularitiesdue to temperature differences between the LED array chips.

Next, a second embodiment of the invention will be described.

The current mirror circuit 580 in the first embodiment does not have anextremely high output impedance, because the drain currents of the threeMOS transistors M₁, M₂, and M₃ are directly affected by differences intheir drain potentials. Different drain potentials can thus createdifferences between the currents supplied to the bipolar transistorsthat sense the temperature T. In the second embodiment, these currentdifferences are reduced by use of a cascoded current mirror circuitconfiguration, which has a higher output impedance.

The second embodiment replaces the temperature-sensing circuit of FIG.27 with the temperature-sensing circuit shown in FIG. 28, comprising npnbipolar transistors Q₁ and Q₂, resistors R₀, R₁, and R₃, and p-channelMOS transistors M₁ to M₆.

The source terminals of MOS transistors M₄, M₅, and M₆ are coupled tothe power supply V_(DD). The gate terminals of MOS transistors M₄, M₅,and M₆ are connected in common to the drain terminal of MOS transistorM₅. The drain terminals of MOS transistors M₄, M₅, and M₆ are coupled tothe source terminals of MOS transistors M₁, M₂, and M₃, respectively.The gate terminals of MOS transistors M₁, M₂, and M₃ are connected incommon to the drain terminal of MOS transistor M₂. MOS transistors M₁ toM₆ form a cascode current mirror circuit 590.

As in the first embodiment, the drain terminals of MOS transistors M₁,M₂, and M₃ are coupled, respectively, to resistor R₁, the collector ofnpn bipolar transistor Q₂, and resistor R₃. Resistor R₀ and npn bipolartransistors Q₁, and Q₂ are interconnected to sense temperature as in thefirst embodiment.

If I₁, I₂, and I₃ are the drain currents of MOS transistors M₁, M₂, andM₃, then as in the first embodiment, the difference ΔV_(BE) between thebase-emitter voltages of transistors Q₁, and Q₂ can be expressed asfollows.

    ΔV.sub.BE =(kT/q)ln(KI.sub.1 /I.sub.2)

MOS transistors M₂ and M₅, which are coupled in series, form a cascodedcurrent source with a higher internal impedance the internal impedanceof M₂ alone. The combined internal impedance of M₁ and M₄ (and of M₃ andM₆) is likewise greater than the internal impedance of M₁ (and M₃)alone. Drain currents I₁ and I₂ (and I₃) therefore remain more nearlyequal despite differences in the drain potentials of MOS transistors M₁and M₂ (and M₃).

Aside from this difference, the second embodiment is identical to thefirst embodiment and operates in the same way, sensing temperature asthe difference in the base-emitter voltages of a pair of bipolartransistors. The high internal impedance of the cascoded current mirrorcircuit 590 reduces differences in the currents supplied from thecurrent mirror, thereby leading to more accurate temperature sensing.

Next, a third embodiment of the invention will be described.

Normally, when the printer's power supply is switched on, the supplyvoltage rises quickly. This abrupt voltage surge creates a transientcondition that injects sufficient charge into the base terminals of thebipolar transistors Q₁ and Q₂ in FIGS. 27 and 28 to enable thesetransistors to turn on, after which a type of positive feedback bringsthe temperature-sensing circuit to its correct operating point. If thepower-supply voltage rises very slowly when the printer is switched on,however, it is possible for the temperature-sensing circuits in FIGS. 27and 28 to remain in a stable state in which bipolar transistors Q₁ andQ₂ and MOS transistors M₁ and M₂ are switched off, and the correctreference voltage V_(ref) is not obtained. The third embodiment adds astarting circuit to the configuration shown in FIG. 27 to assure thatbipolar transistors Q₁ and Q₂ turn on before printing operations begin.

Referring to FIG. 29, the temperature-sensing circuit in the thirdembodiment has the same npn bipolar transistors Q₁ and Q₂, resistors R₀,R₁, and R₃, and current mirror circuit 580 as in the first embodiment.The starting circuit comprises an additional n-channel MOS transistor M₇coupled in parallel with the current mirror circuit 580, more preciselyin parallel with MOS transistor M₁, between the power supply V_(DD) andresistor R₁. The gate terminal of MOS transistor M₇ receives the b₃ -WRwrite command signal.

Transistor M₇ can also be a p-channel MOS transistor of suitabledimensions, if write command signal b₃ -WR is coupled through aninverter.

Instead of write command signal b₃ -WR, write command signal b₀ -WR, orany other signal that is normally inactive but is temporarily activatedat some time before printing begins, could be coupled to the gate oftransistor M₇.

Referring to FIG. 30, suppose that when the HD-LOAD signal goes high (attime a), the reference voltage V_(ref) is still zero, due to anextremely slow rise of V_(DD) at power-up, for example. In this state,MOS transistors M₁, M₂, and M₃ are turned off, bipolar transistors Q₁and Q₂ are also turned off, and the temperature-sensing circuit does notrespond to temperature changes.

While HD-LOAD is high (from time a to time b), compensation data areloaded into the driver ICs. As part of this process, write commandsignal b₃ -WR goes high (operation D), causing MOS transistor M₇ toconduct. Charge is thereby injected through transistor M₇ into the gateterminals of bipolar transistors Q₁ and Q₂, as indicated by the arrow inFIG. 29, bringing the circuit comprising transistors Q₁ and Q₂ into aconducting state. The collector potential of transistor Q₂ accordinglybegins to drop. The gate potential of MOS transistors M₁ and M₂therefore drops, increasing the current flow to the bipolar transistorsfrom the current mirror circuit 580, and moving the temperature-sensingcircuit toward its correct operating point. The reference voltageV_(ref) begins rise, as shown at the bottom of FIG. 30, and reaches astable value before printing actually begins.

The third embodiment assures that the advantages of the first embodimentare obtained regardless of the manner in which the printer is poweredup, by using a command signal generated during the storing ofcompensation data to activate the temperature-sensing circuit beforeprinting actually begins.

Next, a fourth embodiment of the invention will be described.

Referring to FIG. 31, the driver ICs 101 to 126 in the fourth embodimenthave VREF output terminals for output of the reference voltage V_(ref)generated in their internal temperature-sensing circuits. The VREFoutput terminal of one of the driver ICs, preferably a driver IC in themiddle of the array, such as driver IC 113 in the drawing, is coupled tothe connector (not visible) by which the LED head is interfaced to theprinting control unit. The conventional interface shown in FIG. 52 isthus modified by the addition of a V_(ref) signal line between theprinting control unit 1 and LED head 19. The printing control unit 1receives the reference voltage generated by driver IC 113 as a headalarm signal HD-ALM.

The printing control unit monitors the HD-ALM signal, and halts printingif the HD-ALM voltage rises above a first threshold, e.g. by halting thesupply of driving data at the end of the current page. Printing isresumed when the HD-ALM voltage returns to a second threshold,preferably lower than the first threshold.

FIG. 32 shows the temperature-sensing circuit in the fourth embodiment,which is identical to the temperature-sensing circuit in the firstembodiment with the addition of a pad 550 to which the reference voltageV_(ref) is supplied. This pad 550 is coupled to the VREF output terminalof the driver IC.

As explained in the first embodiment, if the temperature of the LEDarray chips in the LED head rises due to heat generated during theprinting process, the driving current supplied to the LED array chips isincreased to compensate for the reduced optical output efficiency of theLEDs. As a result, even more heat may be generated, causing thetemperature to rise still further.

As also explained in the first embodiment, the reference voltage V_(ref)is proportional to the absolute temperature T sensed by thetemperature-sensing circuit.

    V.sub.ref =(R.sub.3 /R.sub.0)(kT/q)ln(K)

The head alarm signal HD-ALM is equal to V_(ref) so by monitoringHD-ALM, the printing control unit 1 monitors the temperature of the LEDhead. If the LED head becomes overheated, due to continuous printing ofall-black pages, for example, the printing control unit can detect thiscondition and halt printing until the temperature of the LED head dropsback to a safe level, thereby preventing damage that might be caused byoverheating.

Conventional LED printers use a thermal fuse to prevent damage fromoverheating. The fourth embodiment enables this fuse to be eliminated.

The fourth embodiment can be modified by supplying the printing controlunit with V_(ref) signals taken from two or more of the driver ICs, orwith an average value or maximum value of these V_(ref) signals.

Next, a fifth embodiment of the invention will be described.

Referring to FIG. 33, the temperature-sensing circuit in the fifthembodiment comprises npn bipolar transistors Q₅₁, Q₅₂, and Q₅₃ withcollectors connected to the power supply V_(DD). The emitter terminal oftransistor Q₅₁ is coupled to ground through a series circuit comprisingresistors R₁₀ and R₁₁. The emitter terminals of transistors Q₅₂ and Q₅₃are coupled to ground through respective resistors R₁₂ and R₁₃. The baseterminals of transistors Q₅₁, Q₅₂, and Q₅₃ are coupled in common to theoutput terminal of an operational amplifier 551. The non-inverting (+)input terminal of operational amplifier 551 is coupled to a pointbetween resistors R₁₀ and R₁₁. The inverting (-) input terminal ofoperational amplifier 551 is coupled to a point between the emitter oftransistor Q₅₂ and resistor R₁₂. Transistors Q₅₁ and Q₅₂ have a sizeratio of N:1 (N>1). To simplify the calculations, in the descriptionbelow it will be assumed that the size ratio of Q₅₂ and Q₅₃ is 1:1, andresistors R₁₂ and R₁₃ have equal resistances.

Resistors R₁₀, R₁₁, R₁₂, and R₁₃ are of the same type, and have equaltemperature coefficients.

The reference voltage V_(ref) generated by this temperature-sensingcircuit will be calculated below, using I₁₁, I₁₂, and I₁₃ to denote theemitter currents of transistors Q₅₁, Q₅₂, and Q₅₃, and V_(R) to denotethe voltage developed across R₁₁. The operational amplifier 551 operatesso as to maintain the following relationship.

    V.sub.R =I.sub.11 R.sub.11 =I.sub.12 R.sub.12

From this relationship,

    I.sub.12 /I.sub.11 =R.sub.11 /R.sub.12

If the base-emitter voltages of transistors Q₅₁ and Q₅₂ are denotedV_(BE1) and V_(BE2), then the difference ΔV_(BE) between them is relatedto R₁₀ as follows.

    I.sub.11 =ΔV.sub.BE /R.sub.10

In addition, ##EQU4## where k is the Boltzmann constant, T is theabsolute temperature of transistors Q₅₁ and Q₅₂, q is the charge of theelectron, I_(S) is the saturation current of transistor Q₅₂, and in isthe natural logarithm function. Furthermore, ##EQU5##

Since R₁₂ =R₁₃, these relationships give V_(ref) as follows. ##EQU6##

Since resistors R₁₀, R₁₁, R₁₂, and R₁₃ have equal temperaturecoefficients, the ratio between the resistance values of two of themdoes not change with temperature. The reference voltage V_(ref) istherefore proportional to the absolute temperature T.

This conclusion also holds if R₁₁ and R₁₂ have mutually equaltemperature coefficients, and R₁₀ and R₁₃ have mutually equaltemperature coefficients.

The fifth embodiment uses the temperature-sensing circuit in FIG. 33 tocompensate for temperature differences between the LED array chips inthe same way as the first embodiment.

Next, a sixth embodiment of the invention will be described. The sixthembodiment provides more complete compensation for the temperaturedependence of the optical output power of the LEDs.

The description of the sixth embodiment will begin with an analysis ofcertain temperature coefficients in the first embodiment, then derivethe temperature coefficient of the driving current needed to hold theoptical output power of the LEDs fixed, and finally present a circuitthat achieves the necessary temperature coefficient.

The reference voltage V_(ref) in each of the preceding embodiments wasrelated to the absolute temperature T by an equation of the followingform, in which C is a constant.

    V.sub.ref =C(kT/q)

Under room temperature conditions, in the vicinity of 300 K, thetemperature coefficient (1/V_(ref))(V_(ref) /T) is substantially 0.33%/°C.

FIG. 34 illustrates the temperature characteristics of LEDs, showingjunction temperature T_(j). in degrees Celsius (° C.) on the horizontalaxis, and LED driving current I_(F) in milliamperes (mA) on alogarithmic scale on the vertical axis. The curves marked P1 to P6represent constant levels of optical output power, which is measured inmicrowatts (μW). These curves P1 to P6 indicate that to hold the opticaloutput of the LEDs at a constant value, the temperature coefficient ofthe driving current should be substantially 0.6%/° C., which isapproximately twice the temperature coefficient of V_(ref).

FIG. 35 is a block diagram of an LED head having a control IC 100,driver ICs 601 to 626, and a bandgap reference IC 630 such as the TL431bandgap reference manufactured by Texas Instruments. The anode terminalof the bandgap reference IC 630 is connected to ground. The cathodeterminal is coupled to shift voltage input terminals V_(SHF) of thedriver ICs 601-626. As described below, there is a combined flow ofcurrent I_(Z) from these terminals V_(SHF) into the bandgap reference IC630.

A feature of the bandgap reference IC 630 is that a constant voltage ismaintained between its anode and cathode terminals over a wide range ofvalues of the current I_(Z). This voltage is also extremely stable withrespect to temperature changes, having a temperature coefficient ofessentially zero. The voltage at the V_(SHF) terminals of the driver ICstherefore has a fixed value (also denoted V_(SHF) below) that does notvary with temperature.

FIG. 36 shows part of the current reference circuit used in the driverICs in place of the circuit shown in FIG. 19 in the first embodiment,comprising an operational amplifier 501 with its inverting inputterminal receiving a reference voltage V_(ref) from, for example, thecircuit shown in FIG. 27 in the first embodiment. As described above,reference voltage V_(ref) has a temperature coefficient of substantially0.33%/° C.

As in the first embodiment, the output terminal of the operationalamplifier 501 provides the output control voltage V_(control), and isalso coupled to the gate of a p-channel MOS transistor 502, the sourceof which is coupled to the power supply. The non-inverting inputterminal of the operational amplifier 501 is coupled to the drain oftransistor 502, and to one terminal of a resistor R_(ref). Differingfrom the first embodiment, the other terminal of resistor R_(ref) iscoupled to the V_(SHF) terminal 631 of the driver IC (or to a bondingpad that is wire-bonded to the V_(SHF) terminal 631).

The current flowing through resistor R_(ref) is denoted I_(ref). Thecurrent I_(Z) flowing into the bandgap reference IC 630 is the sum ofthe I_(ref) currents from all of the driver ICs. As explained above, thebandgap reference IC 630 holds the V_(SHF) terminal 631 at a fixedpotential, regardless of the value of I_(Z).

To describe the operation of the circuit in FIG. 36, the temperaturedependence of the reference current I_(ref) will be calculated below.There is a current mirror relationship between I_(ref) and the LEDdriving current I_(LED), so the temperature coefficient of I_(ref) isalso the temperature coefficient of I_(LED).

The operational amplifier 501 operates so as to equalize the potentialsof its inverting and non-inverting input terminals. This leads to thefollowing relation.

    I.sub.ref =(V.sub.ref -V.sub.SHF)/R.sub.ref

The temperature coefficient αof I_(ref) can be expressed as follows,where for simplicity the temperature coefficient of resistor R_(ref) isignored. ##EQU7##

To obtain the desired value of α, equal to twice the temperaturecoefficient (1/V_(ref))(V_(ref) /T) of V_(ref), it suffices for thefollowing condition to be satisfied.

    V.sub.SHF =(1/2)V.sub.ref

That is, V_(SHF) should be set to about one-half the value of V_(ref)(in the range of temperatures from room temperature to the temperatureof the driver IC during operation).

In the sixth embodiment, accordingly, the temperature-sensing circuit inthe driver ICs is designed to generate a reference voltage V_(ref)substantially equal to twice the fixed value of V_(SHF) output by thebandgap reference IC 630. The current reference circuit then compensatesalmost completely for the known temperature coefficient of the opticaloutput of the LEDs, enabling uniform printed output to be obtained atall operating temperatures.

A similar effect could be obtained by providing each driver IC with aninternal circuit generating a voltage equivalent to V_(SHF), and usingthis voltage to shift the level of the reference voltage V_(ref).

Next, a seventh embodiment of the invention will be described.

To compensate for the reduced optical output of the LEDs at hightemperatures, the first embodiment relies on the temperature-sensingcircuit to generate a reference voltage V_(ref) that increases inproportion with increasing temperature. It is possible, however, forinadequate electrical characteristics of the semiconductor circuitelements used in the temperature-sensing circuit (for example, too smallan Early voltage) to lead to unwanted variations in the referencevoltage V_(ref). Since the seventh embodiment is directed towardimprovements in this regard, the description will begin with a moredetailed explanation of the cause of these variations.

The temperature-sensing circuit in FIG. 27 in the first embodiment usestwo npn bipolar transistors of different physical sizes, and sensestemperature by detecting the difference between their base-emittervoltages. This sensing method implicitly assumes that the collectorcurrents of the bipolar transistors are related mainly to theirbase-emitter voltages, and are substantially independent of thecollector-emitter voltage, or in other words, that the bipolartransistors have sufficiently high Early voltages V_(A).

The bipolar transistors employed, however, are lateral transistorsformed in a semiconductor substrate, and for various reasons, thelateral transistor fabrication process does not yield a high Earlyvoltage. One reason is the unavoidably large width of the base regions.Another reason is the relatively high sheet resistance of the collectorand emitter regions.

FIG. 37 shows that if a sufficiently high Early voltage V_(A) can beobtained, the reference voltage V_(ref) (shown on the vertical axis)will depend very little on the supply voltage V_(DD) (shown on thehorizontal axis). If the Early voltage V_(A) is not sufficiently high,however, the reference voltage V_(ref) varies considerably with thesupply voltage V_(DD).

FIG. 38 plots the V_(DD) dependency of V_(ref) (shown in percent on thevertical axis) against the Early voltage V_(A) (shown on the horizontalaxis), showing that the dependency rises sharply at small values ofV_(A).

The seventh embodiment provides a temperature-sensing circuit andcompensation circuit from which an output voltage that depends onlyslightly on the power-supply voltage can be obtained, even if bipolartransistors with small Early voltages are used.

FIG. 39 shows the temperature-sensing circuit used in the seventhembodiment in place of the circuit in FIG. 27 in the first embodiment.

The circuit in FIG. 39 is generally similar to the circuit in FIG. 27,comprising three p-channel MOS transistors M₇₁, M₇₂, and M₇₃ forming acurrent mirror, a pair of npn bipolar transistors Q₇₀ and Q₇₁, andresistors R₇₀, R₇₁, and R₇₃. These elements are interconnected in thesame way as the corresponding elements in FIG. 27, but in FIG. 39 anadditional npn bipolar transistor Q₇₂ is inserted in series between MOStransistor M₇₂ and npn bipolar transistor Q₇₁, and an auxiliary powersupply V_(B) is provided to bias the base terminal of transistor Q₇₂.The collector of transistor Q₇₂ is coupled to the drain of MOStransistor M₇₂, and the emitter of transistor Q₇₂ is coupled to thecollector of transistor Q₇₁.

Since the collector of transistor Q₇₀ is coupled to the base oftransistor Q₇₁, the collector-emitter voltage V_(CE) of transistor Q₇₀is equal to the base-emitter voltage V_(BE) of transistor Q₇₁. Thisvoltage changes very little even if the power-supply voltage V_(DD)fluctuates greatly.

Since the collector of transistor Q₇₁ is coupled to the emitter oftransistor Q₇₂, the collector potential of transistor Q₇₁ is equal tothe emitter potential of transistor Q₇₂. This potential, denotedV_(CE2), is related to the base potential V_(B) and the base-emitterpotential V_(BE3) of transistor Q₇₂ as follows.

    V.sub.CE2 =V.sub.B -V.sub.BE3

Accordingly, if V_(B) is substantially equal to twice V_(BE), thecollector-emitter voltages of transistors Q₇₀ and Q₇₁ can be made morenearly equal, and can be held substantially constant despite largefluctuations in the V_(DD) voltage. Transistor Q₇₂ thus shields thecollector potential of transistor Q₇₁ from fluctuations in the powersupply V_(DD).

FIG. 40 shows the seventh embodiment in more detail by showing anauxiliary power supply circuit G_(vb1) that can be used to generate thebase bias voltage V_(B). This circuit is somewhat similar to the circuitemployed for temperature detection in the first embodiment (FIG. 27).Transistors Q₇₄ and Q₇₅ are npn bipolar transistors with a size ratio of1:K. M₇₄ and M₇₅ are p-channel MOS transistors, the source terminals ofwhich are coupled to the V_(DD) power supply, and the gate terminals ofwhich are interconnected to form a current mirror. The drain oftransistor M₇₅ is coupled to the gates of transistors M₇₄ and M₇₅ and tothe collector of transistor Q₇₅. The drain of transistor M₇₄ is coupledthrough series resistors R₇₅ and R₇₄ to the collector of transistor Q₇₄and the base of transistor Q₇₅. The drain potential of transistor M₇₄ isalso supplied as the bias voltage V_(B) to the base of transistor Q₇₂.

The circuitry external to G_(vb1) in FIG. 40 is identical to FIG. 39.

The base bias voltage V_(B) can be calculated by the same procedure asused in the first embodiment to calculate the drain potential oftransistor M₇₄, obtaining the following result, where V_(BE) nowrepresents the base-emitter voltage of transistor Q₇₄, k is theBoltzmann constant, T is absolute temperature, q is the charge of theelectron, and ln is the natural logarithm function.

    V.sub.B =V.sub.BE +(R.sub.75 /R.sub.74)(kT/q)ln(K)

If K is greater than unity, then the second term on the right has apositive temperature coefficient, whereas the first term on the right(V_(BE)) has a negative temperature coefficient. If appropriate valuesare selected for R₇₄ and R₇₅, the decrease in V_(BE) due to risingtemperature can be balanced by an equal increase in the second term onthe right, making the temperature coefficient of the bias voltage V_(B)negligibly small. Applied to the base of transistor Q₇₂, this biasvoltage controls the rise in the collector potential of transistor Q₇₁and reduces the variability of the output voltage V_(ref) due to theEarly effect.

FIG. 41 illustrates the effect of the seventh embodiment by plotting theoutput voltage V_(ref) in FIG. 40 as a function of the power-supplyvoltage V_(DD) when the Early voltage of the bipolar transistors is tenvolts. Despite this very small Early voltage, the dependency of V_(ref)on V_(DD) is held to only a few percent.

Next, an eighth embodiment of the invention will be described. Theeighth embodiment adds a starting circuit to the configuration of theseventh embodiment, and provides a separate bias circuit to prevent alarge in-rush current from causing start-up errors, by using a reducedbias potential generated by this bias circuit to start the flow ofcurrent in the temperature-sensing circuit.

Referring to FIG. 42, the eighth embodiment has an auxiliary powersupply circuit G_(vb2) similar to the one (G_(vb1)) in the seventhembodiment. This circuit G_(vb2) and the circuitry to its right in thedrawing operate in substantially the same way as the correspondingcircuits in the seventh embodiment, with like elements identified bylike reference numerals.

The eighth embodiment also provides two p-channel MOS transistors M₇₆and M₇₇ to assure start-up even if the power-supply voltage rises veryslowly, as in the third embodiment. The gates of transistors M₇₆ and M₇₇receive the bit₃ -WR write command signal, as inverted by an inverter552. The drain of transistor M₇₆ is coupled to a point betweentransistor M₇₁ and resistor R₇₁, while the drain of transistor M₇₇ iscoupled to a point between transistor M₇₄ and resistor R₇₅.

The sources of transistors M₇₆ and M₇₇ are coupled to a bias circuitGb_(s) comprising a resistor R₇₈ and an n-channel MOS transistor M₇₈coupled in series between the power-supply voltage V_(DD) and ground.The gate and drain of transistor M₇₈ are both coupled to one terminal ofresistor R₇₈, holding the drain potential of transistor M₇₈ to a valueslightly above the threshold voltage of transistor M₇₈, regardless ofvariations in V_(DD). The exact value of the drain potential depends onthe dimensions of transistor M₇₈ and the resistance value of resistorR₇₈. This drain potential is supplied to the sources of transistors M₇₆and M₇₇.

As explained in the third embodiment, when the printer's power isswitched on, if for some reason the power-supply voltage rises extremelyslowly, the transistors in the temperature-sensing circuit may fail toturn on, so that no reference voltage V_(ref) is obtained. Before actualprinting begins, however, the bit₃ -WR signal line goes high during thetransfer of compensation data from the control IC 100 to the driver ICs,turning on MOS transistors M₇₆ and M₇₇ and injecting current from thebias circuit Gb_(s) into the bases of bipolar transistors Q₇₀, Q₇₁, Q₇₄,and Q₇₅.

If current were to be injected directly from the power supply, and ifthe on-resistances of transistors M₇₆ and M₇₇ were small, excessive flowof current into the bases of transistors Q₇₀ and Q₇₄ might saturatethese transistors, reducing the collector potentials of transistors Q₇₀and Q₇₄ to such a low level as to turn off transistors Q₇₁ and Q₇₅. Thisproblem could be prevented by careful design of transistors M₇₆ and M₇₇,but it can also be prevented as in the eighth embodiment, by injectingcurrent from a circuit biased at the desired potential of the injectionpoints (the points between resistors R₇₁ and R₇₅ and transistors M₇₁ andM₇₄).

In the eighth embodiment, the power-supply voltage is divided byresistor R₇₈ and transistor M₇₈ to produce a comparatively lowpotential, which is used as a bias potential for current injection. Whenbit₃ -WR goes high, inverter 552 turns on transistors M₇₆ and M₇₇, andcurrent is injected through resistors R₇₁ and R₇₅ into the bases oftransistors Q₇₀, Q₇₁, Q₇₄, and Q₇₅, but the low bias potential fromwhich this current flows ensures that transistors Q₇₀ and Q₇₄ do notsaturate. All four bipolar transistors Q₇₀, Q₇₁, Q₇₄, and Q₇₅ thus turnon.

When the bit₃ -WR signal goes low, inverter 552 turns transistors M₇₆and M₇₇ off, and positive feedback operates as explained in the thirdembodiment to bring the reference voltage V_(ref) to the desired level.

The eighth embodiment assures that output of the reference voltageV_(ref) starts before printing begins, even if the power-supply voltagerises slowly, without placing exacting requirements on the on-resistancevalues and other parameters of individual transistors.

Next, a ninth embodiment of the invention will be described.

The ninth embodiment provides the driver ICs with a test circuit toshorten the time required for testing the individual driver ICs beforethey are coupled to the LED array chips or mounted in the LED head. Suchunit tests are carried out, for example, before the driver ICs areseparated from the semiconductor wafer on which they are fabricated.Test time is a significant consideration, because the number of LEDs islarge (e.g. 2496), and the driver ICs must provide a separate outputterminal for each driven LED. In the embodiments described above, inwhich the LED output is adjustable in sixteen steps, fully testing adriver IC involves sixteen current measurements at each of the outputterminals. If one current measurement takes only ten milliseconds (10ms), the total measurement time for a single LED head is substantiallyfour hundred seconds.

    10 ms×16×2496≅400 s

The test procedure can be shortened by measuring only some of thesixteen current levels, but since there are five independent drivingtransistors 520 to 524, at least five current measurements are necessaryper LED driving output terminal. The ninth embodiment partially altersthe internal operation of the driver ICs during testing, therebyreducing the test procedure to at most one current measurement per LEDdriving output terminal. The other current measurements are replaced bywindow comparisons, which are less expensive in terms of test time andtest equipment cost.

Referring to FIG. 43, each of the driver ICs 901 to 926 in the ninthembodiment has a test input terminal. The test input terminal can beleft unconnected when the driver ICs are mounted in the LED head.

FIG. 44 is a block diagram showing the internal structure of the driverICs 901 to 926 in the ninth embodiment. The test input terminal ispulled down through a resistor 930 to the ground level, so when the testinput terminal is left unconnected, the test input signal is held at thelow logic level. When the test input terminal is connected to externaltest equipment, the test equipment supplies a test signal to the testinput terminal. The test signal is passed to each of the drivingcircuits 230d.

FIG. 45 shows one of the driving circuits 230d, using the same referencenumerals as in FIG. 20 for equivalent circuit elements. The new elementsare an inverter 931 that inverts the TEST-P signal received from thetest input terminal, an AND gate 932 that replaces the buffer circuit509 of the first embodiment, and a resistor 933 coupled between theoutput terminal 525 and ground. The two input terminals of AND gate 932receive the signals output by AND gate 504 and inverter 931. Resistor933 is not part of the driver IC, but is connected to the outputterminal 525 during the unit test process. Current flowing throughresistor 933 produces a voltage V_(OH) at output terminal 525.

Voltage V_(OH) is supplied to a window comparator in the test equipment(not visible) used to perform the unit test. The window comparatordetermines whether V_(OH) is within a predetermined range or window,such as a window extending several percent above and below apredetermined nominal value. If V_(OH) is not within the window, thedriver IC can be rejected without the need for accurate measurement ofthe actual current value.

FIG. 46 illustrates the operation of the driving circuit in FIG. 45 whenLATCH-DOTn and LED-DRV-ON are high but the TEST-P input signal is low.The output of inverter 931 is high, so AND gate 932 operates in the sameway as the buffer circuit 509 in the first embodiment. When LATCH-DOTnand LED-DRV-ON are both active (high), the output of AND gate 504 goeshigh, the output of AND gate 932 goes high, transistor 514 turns off,and transistor 519 turns on, supplying the V_(control) potential to thegate of the main driving transistor 524. Transistor 524 supplies acurrent determined by the V_(control) potential to the output terminal525. Transistors 520, 521, 522, and 523 supply additional current tooutput terminal 525 responsive to the logic levels of compensation databits b₃ to b₀, in amounts determined by V_(control) and the dimensionsof transistors 520, 521, 522, and 523.

V_(OHO) in FIG. 46 indicates the potential of the output terminal 525when bits b₀ to b₃ are all low, so current is supplied to resistor 933only through the main driving transistor 524. ΔV indicates the increasein the potential of output terminal 525 when b₀ is high and b₁, b₂, andb₃ are low. Similarly, 2ΔV, 4ΔV, and 8ΔV indicate the increase in thepotential of output terminal 525 when each data compensation bit b₁, b₂,and b₃ goes high independently, while the other three data compensationbits are low. ΔV is the product of the driving current supplied by MOStransistor 523 and the resistance of resistor 933.

As explained in the first embodiment, differences in LED output arisingfrom variability in the fabrication process are corrected by using bitsb₀ to b₃ to adjust the driving current in, for example, two-percentsteps, with sixteen adjustment levels. The voltage V_(OH) acrossresistor 933 is proportional to the driving current, and ΔV is, in theabove example, two percent of V_(OHO). Thus the change in V_(OH) causedby switching b₀ on or off is only two percent, which is less than theallowed variability in V_(OHO). Detecting this two-percent change with awindow comparator would be impractical.

FIG. 47 illustrates the operation when the TEST-P signal is high. Theoutputs of inverter 931 and AND gate 932 are both low, switchingp-channel MOS transistor 514 on and n-channel MOS transistor 519 off, sothat the gate-source voltage of the main driving transistor 524 issubstantially zero and transistor 524 is switched off. The voltageV_(OHO) that was indicated in FIG. 46 is therefore not present in FIG.47.

When compensation data bits b₀ to b₃ are all low, the potential V_(0H)observed at the output terminal 525 is zero volts. When b₀ to b₃ aredriven high one bit at a time, potentials V_(OH) equal to ΔV, 2ΔV, 4ΔV,and 8ΔV are observed at output terminal 525. Each compensation data bitnow produces a relatively large potential change, which can easily bedetected by the window comparator in the test equipment.

The test procedure in the ninth embodiment will be described withreference to FIGS. 48 and 49, using the same notation as in FIG. 25 inthe first embodiment. The input signal at the SEL terminal of the driverIC is assumed to be at the high logic level.

First, all-zero compensation data are loaded into the compensationmemory. Referring to FIG. 48, an active (high) HD-LOAD signal is appliedto the LOADI terminal from time a to time b, during which interval thedata signals (HD-DATA₃ to HD-DATA₀) are all held at the low logic level.During this interval, first, twenty-four clock pulses (HD-CLK) aresupplied to the CLKI input terminal (B), loading all-zero data into theshift register 230a in the driver IC. Three HD-STB-N pulses are thensupplied to the STB input terminal (C), generating a bit₃ -WR writecommand signal (D) that writes all-zero data into memory cell c3 in eachof the compensation memory circuits shown in FIG. 16.

Further clock pulses (E, H, and K) and strobe pulses (F, I, and L) aresupplied to write all-zero data into the other memory cells (c2, c1, c0)in the memory compensation circuits, then the HD-LOAD signal is returnedto the low logic level. The TEST-P input signal can be held lowthroughout the loading of these all-zero data.

Next, with TEST-P low, HD-LOAD and HD-STB-N are driven so as to transferdriving data and activate each of the LED driving circuits 230d. In FIG.45, LATCH-DOTn and LED-DRV-ON go high. The resulting driving currentscan be measured by accurately measuring the voltage V_(OH) at eachoutput terminal 525. Alternatively, the window comparator can be used todetermine quickly whether each driving current is in an acceptablerange. The measured or compared driving current is due only to the maindriving transistor 524. The other driving transistors 520 to 523 remainoff, because bits b₀ to b₃ of the compensation data area all zero. Thispart of the procedure tests for normal operation of the main drivingtransistor 524 and its associated circuitry, including the currentreference circuit 247.

Next, to test the other driving transistors 520 to 523 and theirassociated circuits, the TEST-P signal is set to the high logic level,and bits b₀ to b₃ are driven high one at a time. FIG. 49 shows theprocedure for loading high data for bit b₀, to test for short circuits,open circuits, and other faults in memory cell c0 in FIG. 16(transistors 471 and 472 and inverters 451 and 452 in FIG. 18), and ANDgate 508 and transistors 513, 518, and 523 in FIG. 45.

The HD-LOAD signal is driven high from time a to time b in FIG. 49.During the HD-CLK, HD-STB-N, and DATA-WR waveform segments marked B toJ, the HD-DATA signals are held low and all-zero data are written intomemory cells c3, c2, and c1 in the compensation memory circuits. Duringthe HD-CLK waveform segment marked K, comprising twenty-four clockpulses, the HD-DATA signals are all driven high, loading all-one datainto the shift register 230a. The HD-STB-N pulses (L) and bit₀ -WRsignal (M) then write the all-one data into the c0 memory cells in thecompensation memory circuits.

After HD-LOAD goes low at time b, TEST-P is driven high, dot data aresupplied, then HD-STB-N is driven low, and the potentials of the LEDdriving output terminals 525 are sensed by the window comparator in thetest equipment. Referring again to FIG. 45, since TEST-P is high, theoutput of AND gate 932 is low, and the main driving transistor 524 isswitched off, but the b₀ signal is now high, so when LATCH-DOTn andLED-DRV-ON go high, the outputs of both AND gates 504 and 508 go high,switching on transistor 523. Since b₁, b₂, and b₃ are low, transistors522, 521, and 520 remain off.

The potential V_(OH) of the output terminal 525 should accordingly beΔV, as shown in FIG. 47. If the circuits that generate this ΔV outputare defective, then V_(OH) will generally either be zero volts or have avalue of 3ΔV or greater. For example, if the b₁ input to AND gate 507 inFIG. 25 is shorted to V_(DD), the output potential will be ΔV+2ΔV, whichis 3ΔV. Similarly, if b₂ or b₃ is shorted to V_(DD), the outputpotential will be 5ΔV or 9ΔV. The window comparator in the testequipment can easily detect the difference between ΔV and zero volts, orbetween ΔV and 3ΔV, so faults such as these can be discovered withoutaccurate current measurements.

The ninth embodiment greatly reduces the number of accurate currentmeasurements needed to test the current reference circuit and drivingcircuits in the driver IC, enabling most such measurements to bereplaced by quicker and less expensive window comparisons. The ninthembodiment thus enables test times to be shortened and fabrication coststo be reduced.

Next, a tenth embodiment of the invention will be described. The tenthembodiment relates to a method of mounting the LED array chips anddriver ICs of the ninth embodiment.

The LED array chips in the tenth embodiment are semiconductor chips withanode terminals for driving the individual LEDs on one surface, and acommon cathode terminal on the other surface. Each LED array chip isbonded directly to the corresponding driver IC, the anode terminals ofthe LEDs being aligned with and electrically coupled to thecorresponding driving terminals of the driver IC, which is mounted on aprinted circuit board. The common cathode is coupled by bonding wires tothree dummy terminals provided on the driver IC. The dummy terminals arecoupled by further bonding wires to ground terminals on the printedcircuit board.

FIG. 50 is a sectional view showing the printed circuit board 560, adriver IC 561, an LED array chip 562, a first bonding wire 563 couplingthe common cathode (CC) on the upper surface 562b of the LED array chip562 to one of the dummy terminals on the driver IC 561, and a secondbonding wire 564 coupling the dummy terminal to a ground terminal on theprinted circuit board 560. The dummy terminal is a rectangularwire-bonding pad having substantially twice the surface area of thewire-bonding pads (not visible) used for input/output signals, toprovide sufficient space for attachment of both bonding wires 563 and564.

The driver IC 561 also has several driving power supply (V_(DD))terminals, one of which is shown in the drawing. Each of these V_(DD)terminals is a bonding pad that is coupled by a bonding wire (notvisible) to a V_(DD) terminal on the printed circuit board 560.

The driver IC 561 has driving output terminals DO1 to DO96, which arearranged zig-zag in a double row. Each of these driving terminals is theoutput terminal 525 of one driving circuit in the driver IC. The LEDsare formed on the lower surface 562a of the LED array chip, and haveanode terminals, denoted AX, which are disposed in a similar double rowfacing the driving output terminals DO1 to DO96. The LEDs emit light inthe direction of the arrow marked LG.

The LED array chip 562 is bonded to the driver IC 561 by an epoxy-basedadhesive (ADH) in which tiny gold or gold-plated granules are dispersed.Some of these gold granules come to be positioned between the anodeterminals AX of the LEDs and the driving output terminals DO1 to DO96 ofthe driver IC 561. When the LED array chip 562 is pressed down onto thedriver IC 561, these gold granules form electrical couplings between theanode terminals AX and driving output terminals DO1 to DO96, eliminatingthe need for bonding wires.

Referring to FIG. 51, the driver IC 561 has a row of wire-bondingterminals arranged along one side (the right side in the drawing), withrectangular dummy terminals in the two corners and in the center of thisside, enabling the common cathode of the LED array chip 562 to begrounded at three widely separated points. The dummy terminal markedDUMMY/TEST in the bottom right corner in FIG. 51 is also used as thetest input terminal. The other (smaller, square) wire-bonding terminalson this side are DATAI₀ to DATAI₃, CLKI, LOADI, V_(DD), STB, GND, SEL,VREF, LOADO, CLKO, and DATAO₀ to DATAO₃. The two V_(DD) terminals andtwo GND terminals supply power and ground potentials to the logiccircuits in the driver IC 561.

All three dummy terminals, including DUMMY/TEST, are coupled by bondingwires to ground terminals on the printed circuit board 560. TheDUMMY/TEST terminal is accordingly held at the ground level, keeping theTEST-P signal inactive so that it does not interfere with printingoperations.

The four V_(DD) terminals in the center of the driver IC 561 are used tosupply LED driving current to the LED driving circuits. The LED drivingoutput terminals DO1 to DO96 are arranged in a zig-zag pattern along theside opposite to the other signal terminals.

In the tenth embodiment, the DUMMY/TEST terminal used for test signalinput during unit testing of the driver ICs, before they are mounted inthe LED head, is also used for grounding of the common cathode of theLED array chip after mounting in the LED head. This arrangement avoidsthe need for a special test input terminal, thereby reducing the sizeand cost of the driver ICs.

The preceding embodiments have been described in relation to an LEDprinter, but temperature-sensing circuits similar to those shown in theembodiments can also be used in thermal printers, in which the drivenelements are resistive heating elements, and in various other circuits,such as the integrated circuits used to provide driving energy todisplay elements in display devices.

More generally, the invented temperature-sensing circuit can beincorporated into any integrated circuit that needs to detect either itsown temperature or the temperature of a nearby external circuit, whichmight be another integrated circuit, or some other type of electronic oroptical device. The invented temperature-sensing circuit can be used todetect abnormal conditions, so that circuit operations can be shut downif necessary, or to adjust circuit operations within a range of normaltemperature conditions, as in the embodiments above, for temperaturecompensation purposes or other purposes.

A particular advantage of the invention is that the circuitry needed fortemperature compensation of a driven element, or an array of drivenelements, can be built directly into the integrated circuit that drivesthe driven element, or array of driven elements. When the drivenelements are disposed on a plurality of semiconductor chips,incorporation of the invented temperature-sensing circuit into thedriver ICs of these chips can provide automatic compensation fortemperature differences between the driven chips. If the driver ICsalready contain circuitry for compensating for fabrication variabilityby varying the driving current or driving energy, the inventedtemperature-sensing circuit can be added to these compensation circuitsto provide temperature compensation as an additional feature, as in thepreceding embodiments.

The embodiments described above can be combined in various ways. Forexample, the cascoded current mirror circuit of the second embodimentcan be combined with the starting circuit of the third embodiment or theeighth embodiment.

Those skilled in the art will recognize that the embodiments describedabove can be modified in various other ways within the scope of theinvention as claimed below.

What is claimed is:
 1. A temperature-sensing circuit, comprising:a firstbipolar transistor exposed to a temperature to be sensed; a secondbipolar transistor exposed to said temperature to be sensed, differingin size from said first bipolar transistor, and generating a transistoroutput signal; a converting element for converting current to voltage,thereby generating a voltage output signal of the temperature-sensingcircuit; and a current mirror circuit coupled to said first bipolartransistor, said second bipolar transistor, and said converting element,having a plurality of MOS transistors supplying mutually correspondingcurrents to said first bipolar transistor, said second bipolartransistor, and said converting element responsive to said transistoroutput signal, thereby determining base-emitter voltages of said firstbipolar transistor and said second bipolar transistor.
 2. Thetemperature-sensing circuit of claim 1, wherein said current mirrorcircuit has a cascoded circuit configuration.
 3. The temperature-sensingcircuit of claim 1, further comprising a starting circuit for turning onsaid first bipolar transistor and said second bipolar transistor byinjecting charge into said first bipolar transistor and said secondbipolar transistor, responsive to a command signal.
 4. Thetemperature-sensing circuit of claim 3, wherein said starting circuitcomprises a MOS transistor coupled to said first bipolar transistor inparallel with said current mirror circuit, having a gate terminal forreceiving said command signal.
 5. The temperature-sensing circuit ofclaim 3, wherein said starting circuit receives a power-supply voltageand a ground potential, generates an intermediate potential between saidpower-supply voltage and said ground potential, and uses saidintermediate potential to inject said charge into said first bipolartransistor and said second bipolar transistor.
 6. Thetemperature-sensing circuit of claim 1, wherein:said first bipolartransistor and said second bipolar transistor are npn bipolartransistors with grounded emitter terminals, also having respective baseterminals and respective collector terminals; said current mirrorcircuit comprises a first p-channel MOS transistor, a second p-channelMOS transistor, and a third p-channel MOS transistor having respectivesource terminals coupled to a power supply, having respective drainterminals, and having respective gate terminals coupled in common to thedrain terminal of said second p-channel MOS transistor and the collectorterminal of said second bipolar transistor, the drain terminal of saidthird p-channel MOS transistor being coupled to said converting element;further comprisinga first resistor having a first terminal coupled tothe drain terminal of said first p-channel MOS transistor, and a secondterminal coupled to the base terminal of said first bipolar transistor;and a second resistor having a first terminal coupled to the secondterminal of said first resistor, and a second terminal coupled to thecollector terminal of said first bipolar transistor and the baseterminal of said second bipolar transistor.
 7. The temperature-sensingcircuit of claim 6, wherein said converting element comprises a thirdresistor having a first terminal coupled to the drain terminal of saidthird p-channel MOS transistor, and having a grounded second terminal,said second resistor and said third resistor having substantially equaltemperature coefficients.
 8. The temperature-sensing circuit of claim 6,wherein said current mirror circuit also comprises:a fourth p-channelMOS transistor coupled in series between said first p-channel MOStransistor and said power supply; a fifth p-channel MOS transistorcoupled in series between said second p-channel MOS transistor and saidpower supply; and a sixth p-channel MOS transistor coupled in seriesbetween said third p-channel MOS transistor and said power supply; saidfourth p-channel MOS transistor, said fifth p-channel MOS transistor,and said sixth p-channel MOS transistor having mutually interconnectedgate terminals.
 9. The temperature-sensing circuit of claim 6, furthercomprising:a third bipolar transistor coupled in series between thecollector terminal of said second bipolar transistor and the drainterminal of said second p-channel MOS transistor.
 10. Thetemperature-sensing circuit of claim 9, wherein said third bipolartransistor has an emitter terminal coupled to the collector terminal ofsaid second bipolar transistor, a collector terminal coupled to thedrain terminal of said second p-channel MOS transistor, and a baseterminal receiving a certain bias voltage.
 11. The temperature-sensingcircuit of claim 10, further comprising a biasing circuit for generatingsaid bias voltage, said biasing circuit having:a seventh p-channel MOStransistor having a source terminal coupled to said power supply, adrain terminal coupled to the base terminal of said third bipolartransistor, for supplying said bias voltage to the base terminal of saidthird bipolar transistor, and a gate terminal; an eighth p-channel MOStransistor having a source terminal coupled to said power supply, adrain terminal coupled to the gate terminal of said seventh p-channelMOS transistor, and a gate terminal also coupled to the gate terminal ofsaid seventh p-channel MOS transistor; a fourth bipolar transistorhaving a grounded emitter terminal, a base terminal, and a collectorterminal coupled to the drain terminal of said eighth p-channel MOStransistor; a fifth bipolar transistor having a grounded emitterterminal, a base terminal, and a collector terminal coupled to the baseterminal of said fourth bipolar transistor; a fourth resistor having afirst terminal coupled to the drain terminal of said seventh p-channelMOS transistor, and a second terminal coupled to the base terminal ofsaid fifth bipolar transistor; and a fifth resistor having a firstterminal coupled to the second terminal of said fourth resistor, and asecond terminal coupled to the collector terminal of said fifth bipolartransistor.
 12. The temperature-sensing circuit of claim 11, furthercomprising a starting circuit for supplying current to the firstterminal of said first resistor and the first terminal of said fourthresistor, responsive to a command signal.
 13. The temperature-sensingcircuit of claim 12, wherein said starting circuit comprises:a voltagedividing circuit for generating a divided voltage by dividing a voltageof said power supply; a first switching element coupled to said voltagedividing circuit, for supplying said divided voltage to the firstterminal of said first resistor, responsive to said command signal; anda second switching element coupled to said voltage dividing circuit, forsupplying said divided voltage to the first terminal of said fourthresistor, responsive to said command signal.
 14. A temperature-sensingcircuit, comprising:a first bipolar transistor exposed to a temperatureto be sensed; a second bipolar transistor exposed to said temperature tobe sensed, differing in size from said first bipolar transistor; aconverting element for converting current to voltage, thereby generatinga voltage output signal of the temperature-sensing circuit; anoperational amplifier coupled to said first bipolar transistor and saidsecond bipolar transistor, for generating an amplifier output signalresponsive to a difference between respective base-emitter voltages ofsaid first bipolar transistor and said second bipolar transistor; and athird bipolar transistor coupled to said converting element and saidoperational amplifier, for supplying current to said converting elementresponsive to said amplifier output signal.
 15. The temperature-sensingcircuit of claim 14, wherein said first bipolar transistor, said secondbipolar transistor, and said third bipolar transistor are npn bipolartransistors having respective emitter terminals, respective baseterminals receiving said amplifier output signal, and respectivecollector terminals coupled to a power supply, further comprising:afirst resistor having a first terminal coupled to the emitter terminalof said first bipolar transistor and a second terminal coupled to oneinput terminal of said operational amplifier; a second resistor having afirst terminal coupled to the second terminal of said first resistor,and having a grounded second terminal; and a third resistor having afirst terminal coupled to the emitter terminal of said second bipolartransistor and to another input terminal of said operational amplifier,and having a grounded second terminal; said first resistor and saidsecond resistor having substantially equal temperature coefficients. 16.The temperature-sensing circuit of claim 15, wherein said convertingelement is a fourth resistor having a first terminal coupled to theemitter terminal of said third bipolar transistor, having a groundedsecond terminal, and having a temperature coefficient substantiallyequal to the temperature coefficient of said third resistor.
 17. Adriving apparatus for supplying energy to at least one driven element,comprising:the temperature-sensing circuit of claim 1; and a temperaturecompensation circuit coupled to said temperature-sensing circuit, foradjusting the energy supplied to said driven element responsive to thevoltage output signal generated by said temperature-sensing circuit. 18.The driving apparatus of claim 17, wherein said temperature-sensingcircuit is thermally coupled to said driven element and senses atemperature of said driven element.
 19. The driving apparatus of claim18, wherein said driving apparatus selectively and cyclically drives aplurality of driven elements to form dots, said driven elements generateheat, said driven elements operate with decreasing efficiency atincreasing temperature, and said temperature compensation circuitcompensates for said decreasing efficiency.
 20. The driving apparatus ofclaim 19, wherein said driven elements are disposed on a plurality ofsemiconductor chips, and said driving apparatus comprises a plurality ofintegrated circuits disposed adjacent respective semiconductor chips,for driving the driven elements on respective semiconductor chips, eachof said integrated circuits separately having said temperature-sensingcircuit and said temperature compensation circuit.
 21. The drivingapparatus of claim 17, further comprising a voltage reference circuitgenerating a constant voltage with a temperature coefficient ofsubstantially zero, said temperature compensation circuit adjusting saiddriving energy according to a difference between said constant voltageand the voltage output signal generated by said temperature-sensingcircuit.
 22. A driving apparatus for selectively and cyclically drivinga plurality of driven elements to form dots, comprising:thetemperature-sensing circuit of claim 1, for sensing the temperature ofsaid driven elements; a temperature compensation circuit coupled to saidtemperature-sensing circuit, for generating a control voltage responsiveto the voltage output signal generated by said temperature-sensingcircuit; a plurality of driving circuits coupled to said temperaturecompensation circuit, for supplying driving energy to respective drivenelements, responsive to driving data indicating whether said drivenelements are to be driven, to compensation data for adjusting saiddriving energy, and to said control voltage; a plurality of compensationmemory circuits coupled to respective driving circuits, for storing saidcompensation data; and a data transfer means coupled to said pluralityof driving circuits and said plurality of compensation memory circuits,for first transferring said compensation data to said compensationmemory circuits, then transferring said driving data to said drivingcircuits.
 23. A printer comprising the driving apparatus of claim 22.24. The printer of claim 23, further comprising a printing control unitreceiving the voltage output signal from said temperature-sensingcircuit, for halting transfer of said driving data to said drivingcircuits when the voltage output signal generated by saidtemperature-sensing circuit exceeds a certain threshold.
 25. A drivingapparatus for supplying energy to at least one driven element,comprising:the temperature-sensing circuit of claim 14; and atemperature compensation circuit coupled to said temperature-sensingcircuit, for adjusting the energy supplied to said driven elementresponsive to the voltage output signal generated by saidtemperature-sensing circuit.
 26. The driving apparatus of claim 25,wherein said temperature-sensing circuit is thermally coupled to saiddriven element and senses a temperature of said driven element.
 27. Thedriving apparatus of claim 26, wherein said driving apparatusselectively and cyclically drives a plurality of driven elements to formdots, said driven elements generate heat, said driven elements operatewith decreasing efficiency at increasing temperature, and saidtemperature compensation circuit compensates for said decreasingefficiency.
 28. The driving apparatus of claim 27, wherein said drivenelements are disposed on a plurality of semiconductor chips, and saiddriving apparatus comprises a plurality of integrated circuits disposedadjacent respective semiconductor chips, for driving the driven elementson respective semiconductor chips, each of said integrated circuitsseparately having said temperature-sensing circuit and said temperaturecompensation circuit.
 29. The driving apparatus of claim 25, furthercomprising a voltage reference circuit generating a constant voltagewith a temperature coefficient of substantially zero, said temperaturecompensation circuit adjusting said driving energy according to adifference between said constant voltage and the voltage output signalgenerated by said temperature-sensing circuit.
 30. A driving apparatusfor selectively and cyclically driving a plurality of driven elements toform dots, comprising:the temperature-sensing circuit of claim 14, forsensing the temperature of said driven elements; a temperaturecompensation circuit coupled to said temperature-sensing circuit, forgenerating a control voltage responsive to the voltage output signalgenerated by said temperature-sensing circuit; a plurality of drivingcircuits coupled to said temperature compensation circuit, for supplyingdriving energy to respective driven elements, responsive to driving dataindicating whether said driven elements are to be driven, tocompensation data for adjusting said driving energy, and to said controlvoltage; a plurality of compensation memory circuits coupled torespective driving circuits, for storing said compensation data; and adata transfer means coupled to said plurality of driving circuits andsaid plurality of compensation memory circuits, for first transferringsaid compensation data to said compensation memory circuits, thentransferring said driving data to said driving circuits.
 31. A printercomprising the driving apparatus of claim
 30. 32. The printer of claim31, further comprising a printing control unit receiving the voltageoutput signal from said temperature-sensing circuit, for haltingtransfer of said driving data to said driving circuits when the voltageoutput signal generated by said temperature-sensing circuit exceeds acertain threshold.